Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A data storage system, comprising: one or more non-volatile memory devices; and a controller, wherein the controller is configured to: determine whether a command to a first non-volatile memory device of the one or more non-volatile memory devices is dropped; when the command to the first non-volatile memory device is determined to be dropped, update a first counter value indicating a number of commands to the first non-volatile memory device that are dropped; and increase, based on at least one of the first counter value and one or more parameter values of the first non-volatile memory device, a value of a chip-enable setup time parameter for the first non-volatile memory device by a first time duration; and when the command to the first non-volatile memory device is determined to be not dropped, update a second counter value associated with the first non-volatile memory device; determine whether the second counter value satisfies a threshold value; and when the second counter value satisfies the threshold value, decrease the value of the chip-enable setup time parameter for the first non-volatile memory device by a second time duration.
The invention relates to a data storage system designed to improve command reliability in non-volatile memory devices by dynamically adjusting timing parameters based on command drop detection. The system includes one or more non-volatile memory devices and a controller that monitors command execution. When a command to a memory device is dropped, the controller increments a counter tracking dropped commands and increases the chip-enable setup time parameter for that device by a specified duration. This adjustment provides additional time for the memory device to stabilize, reducing the likelihood of future command drops. Conversely, when commands are successfully processed, the controller increments a second counter and checks if it meets a predefined threshold. If the threshold is satisfied, the chip-enable setup time is decreased by another specified duration, optimizing performance by minimizing unnecessary delays. The system dynamically balances reliability and efficiency by adapting timing parameters based on real-time command success rates and device-specific parameters, ensuring robust operation without excessive overhead.
2. The data storage system of claim 1 , wherein the controller is configured to: when the second counter value satisfies the threshold value, determine, based on at least one of one or more of the second counter value, or the one or more parameter values of the first non-volatile memory device, the second time duration.
The invention relates to a data storage system designed to optimize performance and reliability by dynamically adjusting operational parameters based on monitored conditions. The system includes a controller and at least one non-volatile memory device, such as a solid-state drive (SSD) or flash memory. The controller monitors operational parameters of the memory device, such as read/write latency, error rates, or temperature, and uses these parameters to adjust system behavior. A key feature is the use of a counter that tracks specific events or conditions, such as error occurrences or performance degradation. When the counter value reaches a predefined threshold, the controller determines a second time duration based on the counter value or the monitored parameters. This time duration may dictate when to perform maintenance tasks, such as garbage collection, wear leveling, or data migration, to maintain system efficiency and longevity. The system dynamically adapts to changing conditions, ensuring optimal performance while minimizing wear on the memory device. This approach improves reliability and extends the lifespan of the storage system by proactively addressing potential issues before they escalate.
3. The data storage system of claim 1 , wherein the controller is configured to: when the second counter value satisfies the threshold value, determine whether the value of the chip-enable setup time parameter satisfies a default value of the chip-enable setup time parameter; and when the value of the chip-enable setup time parameter does not satisfy the default value of the chip-enable setup time parameter, decrease the value of the chip-enable setup time parameter by the second time duration.
In the field of data storage systems, particularly those involving memory controllers and non-volatile memory devices, a common challenge is optimizing timing parameters to ensure reliable data access while maximizing performance. The invention addresses this by dynamically adjusting a chip-enable setup time parameter based on operational conditions. The system includes a controller that monitors a second counter value, which tracks occurrences of a specific event, such as a timing violation or error. When this counter value meets a predefined threshold, the controller checks whether the current chip-enable setup time parameter matches its default value. If it does not, the controller reduces the parameter by a second time duration, effectively tightening the timing margin to improve performance. This adjustment helps balance speed and reliability in memory operations, particularly in systems where timing parameters are critical for correct data transfer. The invention is part of a broader system that may also include other timing adjustments, such as those based on a first counter value and a first time duration, ensuring comprehensive optimization of memory access timings.
4. The data storage system of claim 1 , wherein the second counter value indicates a number of consecutive commands to the first non-volatile memory device that are not dropped.
A data storage system includes a controller and multiple non-volatile memory devices. The system monitors command execution to the memory devices and tracks performance metrics. A first counter tracks the number of consecutive commands sent to a first non-volatile memory device that are successfully executed without being dropped. A second counter tracks the number of consecutive commands that are not dropped, providing a measure of command reliability. The system uses these counters to assess the health and performance of the memory devices, allowing for predictive maintenance or dynamic adjustments to improve reliability. The counters help identify patterns of command failures or successes, enabling the controller to optimize data storage operations and prevent data loss. The system may adjust command scheduling, error handling, or other parameters based on the counter values to maintain system stability and performance. This approach improves the robustness of the storage system by proactively managing command execution and reducing the risk of data corruption or loss due to dropped commands.
5. The data storage system of claim 1 , wherein the one or more parameter values are based on at least one of manufacturing variance of the first non-volatile memory device and calibration of the first non-volatile memory device.
This technical summary describes a data storage system designed to optimize performance and reliability in non-volatile memory devices by accounting for manufacturing variances and calibration data. The system includes a first non-volatile memory device and a controller configured to manage data storage operations. The controller adjusts one or more parameter values used during these operations based on manufacturing variances of the first non-volatile memory device, such as variations in memory cell characteristics or fabrication inconsistencies. Additionally, the controller incorporates calibration data from the first non-volatile memory device to further refine these parameter values. This calibration data may include measurements or adjustments made during device testing or operation to compensate for deviations from ideal performance. By dynamically adapting to these factors, the system improves data integrity, endurance, and overall efficiency of the non-volatile memory device. The approach ensures that the storage system operates optimally despite inherent manufacturing differences and environmental or operational changes, enhancing reliability and longevity. This solution is particularly relevant in solid-state storage applications where precise control over memory operations is critical.
6. The data storage system of claim 1 , wherein the first time duration is configurable for the first non-volatile memory device, based on at least one of manufacturing variance of the first non-volatile memory device and calibration of the first non-volatile memory device.
A data storage system includes a controller and at least one non-volatile memory device. The system manages data retention by adjusting a first time duration for the first non-volatile memory device based on manufacturing variance or calibration of the device. The first time duration determines when data is refreshed to prevent degradation. The controller monitors the non-volatile memory device to detect performance characteristics, such as error rates or wear levels, and adjusts the refresh timing accordingly. The system may also include multiple non-volatile memory devices, each with configurable time durations tailored to their specific characteristics. The calibration process involves testing the device to determine optimal refresh intervals, while manufacturing variance accounts for differences in production quality. This adaptive approach extends the lifespan of the storage system by ensuring data integrity without unnecessary refresh operations. The system may further include error correction mechanisms to handle data corruption during the refresh process. The overall design improves reliability and efficiency in non-volatile memory storage by dynamically adjusting refresh intervals based on device-specific factors.
7. The data storage system of claim 1 , wherein the controller is configured to: determine whether a command to a second non-volatile memory device of the one or more non-volatile memory devices is dropped; and when the command to the second non-volatile memory device is determined to be dropped, increase, based on at least one of a third counter value and one or more parameter values of the second non-volatile memory device, a value of a chip-enable setup time parameter for the second non-volatile memory device by a third time period, wherein the third time period is different from the first time duration and the third counter value indicates a number of commands to the second non-volatile memory device that are dropped.
A data storage system includes a controller and one or more non-volatile memory devices. The system addresses the problem of command drops in memory operations, which can lead to performance degradation and data integrity issues. The controller monitors commands sent to the non-volatile memory devices and detects when a command to a specific memory device is dropped. Upon detecting a dropped command, the controller adjusts the chip-enable setup time parameter for that memory device. The adjustment is based on either a counter value tracking the number of dropped commands or specific parameter values of the memory device. The setup time is increased by a predefined time period, which differs from other timing adjustments in the system. This dynamic adjustment helps mitigate command drops by ensuring sufficient timing margins for reliable operation. The system improves memory access reliability and performance by adaptively responding to command failures.
8. A computer-implemented method for a data storage system, comprising: determining whether a command to a first non-volatile memory device of one or more non-volatile memory devices is dropped; in response to determining that the command to the first non-volatile memory device is dropped: updating a first counter value indicating a number of commands to the first non-volatile memory device that are dropped; and increasing, based on at least one of the first counter value and one or more parameter values of the first non-volatile memory device, a value of a chip-enable setup time parameter for the first non-volatile memory device by a first time duration, wherein the first time duration is configurable for the first non-volatile memory device; and in response to determining that the command to the first non-volatile memory device is not dropped: updating a second counter value associated with the first non-volatile memory device; determining whether the second counter value satisfies a threshold value; and in response to determining that the second counter value satisfies the threshold value: decreasing the value of the chip-enable setup time parameter for the first non-volatile memory device by a second time duration.
This invention relates to a computer-implemented method for optimizing command handling in a data storage system with multiple non-volatile memory devices. The method addresses the problem of command drops in non-volatile memory devices, which can degrade system performance and reliability. When a command to a first non-volatile memory device is dropped, the system updates a counter tracking the number of dropped commands for that device. It then increases the chip-enable setup time parameter for the device by a configurable time duration to reduce the likelihood of future command drops. The setup time parameter controls the delay before the device processes a command, allowing the system to dynamically adjust timing to improve stability. If a command is not dropped, the system updates a second counter associated with the device. When this counter reaches a predefined threshold, the system decreases the chip-enable setup time parameter by a second time duration, optimizing performance by reducing unnecessary delays. The method dynamically adjusts the setup time based on both the frequency of command drops and device-specific parameters, ensuring efficient and reliable operation of the storage system. This approach balances performance and stability by adaptively tuning timing parameters in response to real-time command handling conditions.
9. The computer-implemented method of claim 8 , further comprising: determining, based on at least one of one or more of the second counter value, or the one or more parameter values of the first non-volatile memory device, the second time duration.
This invention relates to a computer-implemented method for managing data storage in a system with multiple non-volatile memory devices. The method addresses the challenge of efficiently determining optimal time durations for operations in a storage system, particularly when dealing with wear leveling or performance optimization in non-volatile memory devices. The method involves monitoring one or more parameter values of a first non-volatile memory device, such as wear leveling metrics, performance indicators, or operational status. Additionally, it tracks a second counter value associated with a second non-volatile memory device, which may represent usage cycles, error rates, or other operational metrics. Based on these values, the method calculates a second time duration, which dictates when certain operations (e.g., data migration, wear leveling adjustments, or maintenance tasks) should be performed on the second non-volatile memory device. This ensures balanced usage and prolongs the lifespan of the storage system. The method may also involve comparing the second counter value or parameter values against predefined thresholds to trigger specific actions, such as redistributing data or initiating recovery procedures. By dynamically adjusting operations based on real-time device metrics, the system optimizes performance and reliability while minimizing unnecessary interventions. This approach is particularly useful in solid-state drives (SSDs) and other storage systems where wear leveling and predictive maintenance are critical.
10. The computer-implemented method of claim 8 , further comprising: determining whether the value of the chip-enable setup time parameter satisfies a default value of the chip-enable setup time parameter; and in response to determining that the value of the chip-enable setup time parameter does not satisfy the default value of the chip-enable setup time parameter: decreasing the value of the chip-enable setup time parameter by the second time duration.
This invention relates to optimizing chip-enable setup time parameters in computer systems, particularly for improving timing performance in integrated circuits. The problem addressed is the inefficiency in managing chip-enable setup times, which can lead to suboptimal performance or unnecessary delays in data processing. The method involves adjusting a chip-enable setup time parameter based on predefined conditions. First, the system determines whether the current value of the chip-enable setup time parameter meets a default value. If it does not, the system reduces the parameter's value by a second time duration. This adjustment helps fine-tune the timing characteristics of the chip-enable signal, ensuring more efficient data processing and reducing unnecessary latency. The method may also include additional steps such as monitoring the chip-enable signal, measuring the setup time, and dynamically adjusting the parameter to maintain optimal performance. By dynamically adjusting the chip-enable setup time, the system can adapt to varying operational conditions, improving overall system efficiency and responsiveness. This approach is particularly useful in high-performance computing environments where precise timing control is critical.
11. The computer-implemented method of claim 8 , wherein the second counter value indicates a consecutive number of commands to the first non-volatile memory device that are not dropped.
The invention relates to a method for managing command processing in a computer system with non-volatile memory devices, particularly focusing on tracking consecutive commands that are successfully processed without being dropped. In systems where commands sent to non-volatile memory devices may be lost or dropped due to errors, latency, or other issues, it is important to monitor the reliability of command transmission. The method involves maintaining a counter that increments for each consecutive command successfully processed by a first non-volatile memory device without being dropped. This counter provides a metric for assessing the stability and reliability of command transmission to the device. The method may be part of a broader system for optimizing command scheduling, error handling, or performance monitoring in storage systems. By tracking consecutive successful commands, the system can detect patterns, adjust transmission parameters, or trigger corrective actions when drops occur. This approach helps improve data integrity and system performance by ensuring commands are reliably processed. The counter is reset when a command is dropped, allowing the system to restart the consecutive count from zero. This method is particularly useful in high-performance storage environments where command reliability is critical.
12. The computer-implemented method of claim 8 , wherein the threshold value is a timer value, and the first counter value is associated with the first non-volatile memory device.
This invention relates to a computer-implemented method for managing data storage in a system with multiple non-volatile memory devices. The method addresses the challenge of efficiently tracking and managing data access or usage metrics in such systems, particularly to determine when data should be migrated or retired based on predefined criteria. The method involves monitoring a first counter value associated with a first non-volatile memory device. This counter value is incremented or updated based on specific events, such as data access, writes, or other operations involving the memory device. A threshold value, defined as a timer value, is used to compare against the first counter value. When the first counter value reaches or exceeds the timer value, a predefined action is triggered. This action may include migrating data from the first non-volatile memory device to another storage location, retiring the device, or initiating maintenance operations. The method ensures that memory devices are managed proactively, preventing performance degradation or failure due to excessive usage. By using a timer-based threshold, the system can enforce time-based policies for data retention or device lifecycle management. The approach is particularly useful in systems where non-volatile memory devices, such as SSDs or flash storage, require periodic monitoring to maintain reliability and performance. The method may be integrated into storage controllers, operating systems, or dedicated memory management software to automate these processes.
13. The computer-implemented method of claim 8 , further comprising: determining whether a command to a second non-volatile memory device of the one or more non-volatile memory devices is dropped; and in response to determining that the command to the second non-volatile memory device is determined to be dropped: increasing, based on at least one of a third counter value, and one or more parameter values of the second non-volatile memory device, a value of a chip-enable setup time parameter for the second non-volatile memory device by a third time duration, wherein the third time duration is different from the first time duration and the third counter value indicates a number of commands to the second non-volatile memory device that are dropped.
This invention relates to improving command reliability in systems with multiple non-volatile memory devices, particularly when commands are dropped or fail to execute. The problem addressed is ensuring stable operation of memory devices by dynamically adjusting timing parameters when command failures occur. The method involves monitoring command execution across multiple non-volatile memory devices and detecting when a command to a specific device is dropped or fails. Upon detecting a dropped command, the system increases the chip-enable setup time parameter for that device. The adjustment is based on a counter tracking the number of dropped commands for that device and other operational parameters of the device. The increase in setup time is applied by a specific duration, which differs from any previous adjustments, to improve command reliability. This adaptive approach helps mitigate command failures without requiring manual intervention, enhancing system performance and stability in memory-intensive applications. The method is particularly useful in systems where memory devices may experience varying operational conditions or degradation over time.
14. A data storage system, comprising: one or more non-volatile memory devices; means for determining whether a command to a first non-volatile memory device of the one or more non-volatile memory devices is dropped; in response to determining that the command to the first non-volatile memory device is dropped: means for updating a first counter value indicating a number of commands to the first non-volatile memory device that are dropped; and means for increasing, based on at least one of the first counter value and one or more parameter values of the first non-volatile memory device, a value of a chip-enable setup time parameter for the first non-volatile memory device by a first time period; and in response to determining that the command to the first non-volatile memory device is not dropped: means for updating a second counter value associated with the first non-volatile memory device; means for determining whether the second counter value satisfies a threshold value; and in response to determining that the second counter value satisfies the threshold value: means for decreasing the value of the chip-enable setup time parameter for the first non-volatile memory device by a second time period.
A data storage system includes one or more non-volatile memory devices and a mechanism to monitor and adjust command timing to improve reliability. The system tracks whether commands to a memory device are successfully processed or dropped. When a command is dropped, a first counter increments, and the chip-enable setup time—a delay before activating the memory device—is increased by a first time period to reduce future command failures. This adjustment is based on the counter value and device parameters like performance metrics or error rates. If a command is not dropped, a second counter increments. Once this counter reaches a threshold, the chip-enable setup time is decreased by a second time period to optimize performance. The system dynamically balances reliability and speed by adjusting timing parameters based on real-time command success rates and device conditions. This approach helps mitigate errors in high-speed memory operations while maintaining efficiency.
15. The data storage system of claim 14 , comprising: means for determining, based on at least one of one or more of the second counter value, or the one or more parameter values of the first non-volatile memory device, the second time period.
A data storage system includes a controller and multiple non-volatile memory devices, such as solid-state drives (SSDs) or flash memory. The system monitors performance and health metrics of these devices, including error rates, wear levels, and operational parameters like temperature or voltage. The controller tracks these metrics using counters and parameter values stored in each device. To optimize performance and longevity, the system dynamically adjusts operational parameters, such as read/write thresholds or refresh intervals, based on the monitored data. The system also determines a second time period for performing maintenance operations, such as garbage collection or data scrubbing, by analyzing the counter values or parameter values of the non-volatile memory devices. This ensures that maintenance is performed at optimal intervals, reducing wear and improving reliability. The system may also compare performance metrics across devices to balance workloads and prevent premature failure. The overall goal is to extend the lifespan of the storage devices while maintaining data integrity and performance.
16. The data storage system of claim 14 , comprising: means for determining whether the value of the chip-enable setup time parameter satisfies a default value of the chip-enable setup time parameter; and in response to determining that the value of the chip-enable setup time parameter does not satisfy the default value of the chip-enable setup time parameter: means for decreasing the value of the chip-enable setup time parameter by the second time period.
A data storage system includes a mechanism to adjust a chip-enable setup time parameter, which is a timing parameter used to ensure proper synchronization between a controller and a memory chip. The system monitors this parameter to verify whether its current value matches a predefined default value. If the parameter does not satisfy the default value, the system reduces the parameter by a second time period. This adjustment helps optimize memory access timing, improving performance and reliability. The system may also include additional mechanisms to adjust other timing parameters, such as a chip-enable hold time parameter, which is reduced by a first time period if it does not match its default value. These adjustments are part of a broader process to fine-tune memory interface timing, ensuring efficient data transfer while maintaining signal integrity. The system may further include a controller that executes these adjustments based on detected conditions, such as changes in operating conditions or performance metrics. The overall goal is to dynamically adapt memory timing parameters to enhance system performance and reduce errors.
17. The data storage system of claim 14 , comprising: means for determining whether a command to a second non-volatile memory device of the one or more non-volatile memory devices is dropped; and in response to determining that the command to the second non-volatile memory device is determined to be dropped: means for increasing, based on at least one of a third counter value and one or more parameter values of the second non-volatile memory device, a value of a chip-enable setup time parameter for the second non-volatile memory device by a third time period, wherein the third time period is different from the first time period and the third counter value indicates a number of commands to the second non-volatile memory device that are dropped.
A data storage system includes non-volatile memory devices and manages command processing to improve reliability. The system monitors command drops to specific memory devices and adjusts timing parameters in response. When a command to a second non-volatile memory device is detected as dropped, the system increases the chip-enable setup time parameter for that device. The adjustment is based on either a counter tracking the number of dropped commands or specific operational parameters of the memory device. The increase is applied over a third time period, which differs from a previously used first time period. This adaptive timing adjustment helps mitigate command failures by dynamically optimizing signal timing for the affected memory device. The system ensures reliable operation by continuously monitoring and adjusting parameters to reduce errors in command processing. The approach is particularly useful in storage systems where non-volatile memory devices may experience varying performance conditions.
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August 18, 2020
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