Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A processor unit configured to search, within a target character string, for a reference character string, the processor unit comprising a plurality of vector registers each including a number of vector elements each configured to contain a character, the processor unit further comprising: a matrix of comparators configured to perform a comparison of characters of a reference string stored in a first register of the plurality of vector registers with characters of a target string stored in a second register of the plurality of vector registers; a plurality of logic gates each associated with a respective diagonal of a region of the matrix of comparators, each logic gate of the plurality of logic gates configured to combine the results of comparators located along the respective diagonal of the matrix of comparators, the plurality of logic gates configured to produce a bit vector indicating at least one item selected from the group consisting of: characters of the target string that fully match characters of the reference string and characters of the target string that partially match characters of the reference string; and logic configured to generate, using the resulting bit vector, an indication of a substring of the target string that matches a portion of the reference string, the indication including the beginning of the substring and the length of the substring.
This invention relates to a processor unit designed to efficiently search for a reference character string within a target character string using vectorized parallel processing. The problem addressed is the computational inefficiency of traditional string-matching algorithms, which often require sequential comparisons. The processor unit leverages a plurality of vector registers, each containing multiple vector elements that store individual characters. A matrix of comparators performs parallel comparisons between characters of the reference string, stored in one vector register, and characters of the target string, stored in another vector register. Each comparator outputs a result indicating whether the corresponding characters match. A set of logic gates, each associated with a diagonal of the comparator matrix, combines these results to produce a bit vector. This bit vector identifies either full or partial matches between the target and reference strings. Additional logic processes the bit vector to determine the exact position and length of matching substrings within the target string. The system enables high-speed string searching by exploiting parallel processing capabilities, reducing the time required for pattern matching in applications such as text processing, database searches, and bioinformatics.
2. The processor unit of claim 1 , wherein the target string is a first portion of a larger string, the processor unit further comprising logic configured to: store a second portion of the larger string in a third register of the plurality of vector registers; move, from the second register to the third register, a number of characters equal to the length of the substring, causing the third register to contain a modified portion including the moved characters in conjunction with at least part of the second portion; and compare the modified portion with the reference string.
This invention relates to string processing in computing systems, specifically improving efficiency in handling and comparing portions of larger strings. The problem addressed is the computational overhead and complexity involved in manipulating and comparing substrings within larger strings, particularly in vectorized processing environments. The invention describes a processor unit with vector registers that stores a target string as a first portion of a larger string in a first register. A second portion of the larger string is stored in a third register. The processor unit includes logic to move a number of characters equal to the length of a substring from a second register to the third register. This operation modifies the third register to include the moved characters along with at least part of the second portion. The modified portion is then compared with a reference string. The logic ensures efficient substring manipulation by leveraging vector registers to minimize data movement and processing steps. By storing and modifying portions of the larger string in separate registers, the system avoids redundant operations and optimizes comparison tasks. This approach is particularly useful in applications requiring frequent string operations, such as text processing, data analysis, and pattern matching, where performance and resource efficiency are critical. The invention enhances processing speed and reduces computational overhead by streamlining the handling of string segments within a vectorized architecture.
3. The processor unit of claim 1 , wherein the logic includes: zero-comparison logic configured to generate a first bit vector by comparing the elements of the first register with zeros; and a logic unit configured to: generate a shifted first bit vector by shifting the first bit vector by one bit that corresponds to a character of the reference string; and generate a mask by reversing the order of bits in the shifted first bit vector; and combining logic configured to generate the indication by combining the resulting bit vector with the mask.
This invention relates to a processor unit designed to efficiently compare a data string with a reference string using bitwise operations. The problem addressed is the computational overhead in string comparison tasks, particularly in identifying specific patterns or characters within a data string. The processor unit includes specialized logic to perform these comparisons in hardware, reducing the need for software-based processing and improving performance. The processor unit includes a logic circuit that generates a bit vector by comparing elements of a first register (containing the data string) with zeros. This bit vector indicates which elements in the data string are non-zero. A logic unit then shifts this bit vector by one bit position to align it with a character in the reference string. The shifted bit vector is reversed to create a mask, which is used to filter or modify the original bit vector. The combining logic then merges the resulting bit vector with the mask to produce an indication, such as a match or mismatch between the data string and the reference string. This hardware-based approach accelerates string comparison operations, making it suitable for applications requiring fast pattern matching, such as text processing, data validation, or cryptographic operations. The invention optimizes the comparison process by leveraging bitwise operations, reducing latency and power consumption compared to traditional software-based methods.
4. The processor unit of claim 1 , wherein the plurality of logic gates includes a gate chain configured to perform a logical AND operation between outputs of comparators located along a diagonal of the matrix of comparators.
This invention relates to a processor unit designed for efficient comparison and logical operations in a matrix of comparators. The problem addressed is the need for fast and resource-efficient logical processing in systems requiring simultaneous comparisons and conditional logic operations, such as digital signal processing or parallel computing. The processor unit includes a matrix of comparators arranged to compare multiple input signals in parallel. The comparators generate output signals based on these comparisons. A key feature is the inclusion of a gate chain composed of multiple logic gates, specifically configured to perform a logical AND operation on the outputs of comparators positioned along a diagonal of the matrix. This arrangement allows for efficient extraction of specific logical conditions from the matrix, such as detecting when all comparators along a diagonal meet certain criteria. The gate chain is designed to propagate the AND operation result through the logic gates, ensuring minimal delay and optimal use of hardware resources. This structure is particularly useful in applications where diagonal comparisons are critical, such as in certain types of matrix operations or pattern recognition tasks. The invention improves processing speed and reduces complexity by integrating the AND operation directly into the comparator matrix, eliminating the need for separate logic units.
5. The processor unit of claim 4 , wherein the gate chain includes an AND gate connected to outputs of each adjacent pair of comparators of the diagonal of the matrix of comparators.
This invention relates to a processor unit with a gate chain for evaluating a matrix of comparators, addressing the need for efficient and accurate data processing in digital circuits. The processor unit includes a matrix of comparators arranged in rows and columns, where each comparator generates an output based on input signals. The gate chain is a logical structure that processes these outputs to determine specific conditions or relationships within the matrix. The gate chain includes an AND gate connected to the outputs of each adjacent pair of comparators along a diagonal of the matrix. This configuration allows the processor unit to detect when both comparators in an adjacent pair meet predefined criteria, enabling precise logical operations. The arrangement ensures that the AND gate evaluates the outputs of the adjacent comparators in a coordinated manner, improving the accuracy and efficiency of the processor unit's decision-making process. This design is particularly useful in applications requiring parallel data comparison, such as digital signal processing, error detection, or pattern recognition.
6. The processor unit of claim 1 , the plurality of logic gates further including: zero-detect logic configured to: identify empty vector elements of the first register; and generate a zero-bit vector including logical values indicating the identified empty vector elements and indicating non-empty vector elements; and a logic circuit configured to perform a logical OR operation between each bit value of the zero-bit vector and the output of a corresponding comparator, the corresponding comparator output resulting from a comparison of an vector element stored in the first register to a corresponding vector element stored in the second register.
This invention relates to a processor unit designed to efficiently handle vector operations, particularly for identifying and processing empty vector elements in parallel computations. The problem addressed is the need to optimize vector processing by efficiently detecting and managing empty elements to avoid unnecessary computations and improve performance. The processor unit includes a plurality of logic gates that perform specialized operations on vector data stored in registers. A zero-detect logic identifies empty vector elements in a first register and generates a zero-bit vector, where each bit indicates whether a corresponding vector element is empty or non-empty. This zero-bit vector is used to mask operations, ensuring that only valid (non-empty) elements are processed. Additionally, a logic circuit performs a logical OR operation between each bit of the zero-bit vector and the output of a corresponding comparator. The comparator compares each vector element in the first register to a corresponding element in a second register, producing a result that indicates whether the elements are equal. The logical OR operation combines these results with the zero-bit vector, effectively filtering out comparisons involving empty elements. This ensures that only valid comparisons influence the final output, improving computational efficiency and accuracy. The invention enhances vector processing by dynamically masking invalid elements, reducing unnecessary computations, and improving the reliability of parallel operations. This is particularly useful in applications requiring high-performance vector arithmetic, such as scientific computing, machine learning, and data processing.
7. The processor unit of claim 6 , the logic circuit for performing logical OR operation including a plurality of OR gates, wherein each OR gate of the plurality of OR gates is connected between an AND gate and a respective comparator.
The invention relates to a processor unit designed for efficient logical operations, specifically addressing the need for optimized data processing in digital circuits. The processor unit includes a logic circuit configured to perform logical OR operations using multiple OR gates. Each OR gate in the plurality is directly connected between an AND gate and a corresponding comparator. The AND gate receives input signals and generates an output that is fed into the OR gate, which then processes the signal before passing it to the comparator. The comparator evaluates the processed signal against a reference value, enabling precise decision-making in digital logic operations. This configuration enhances computational efficiency by reducing signal propagation delays and minimizing circuit complexity. The system is particularly useful in applications requiring high-speed data processing, such as digital signal processing, microprocessors, and embedded systems. The invention improves upon prior art by integrating OR gates in a structured manner between AND gates and comparators, ensuring faster and more reliable logical evaluations. The overall design optimizes resource utilization while maintaining accuracy in digital computations.
8. The processor unit of claim 1 , wherein the resulting bit vector comprises: a first bit value at a first bit position marking a beginning of a first substring of the target string, the first substring fully matching the reference string; and a second bit value at a second bit position marking the beginning of a second substring of the target string, the second substring matching a portion of the reference string.
This invention relates to string matching techniques in computing, specifically improving the efficiency of identifying substrings within a target string that match or partially match a reference string. The problem addressed is the computational overhead and complexity of traditional string-matching algorithms, particularly when dealing with large datasets or real-time processing requirements. The invention involves a processor unit that generates a bit vector representing the results of a string-matching operation. The bit vector includes a first bit value at a specific position indicating the start of a substring in the target string that fully matches the reference string. Additionally, the bit vector contains a second bit value at another position marking the beginning of a different substring in the target string that matches only a portion of the reference string. This approach allows for efficient identification of both exact and partial matches, enabling faster processing and reduced computational overhead compared to conventional methods. The bit vector can be used in applications such as text search, pattern recognition, and data compression, where quick and accurate string matching is critical. The invention enhances performance by providing a compact and structured representation of matching results, facilitating rapid analysis and decision-making in various computational tasks.
9. The processor unit of claim 1 , wherein the matrix of comparators includes equality comparators.
A system for high-speed data processing includes a processor unit configured to perform parallel comparisons of data elements. The processor unit contains a matrix of comparators that evaluate multiple data elements simultaneously to identify matches or relationships between them. The matrix of comparators includes equality comparators, which determine whether two or more data elements are identical. These comparators enable rapid decision-making in applications such as data sorting, pattern recognition, or database searches by quickly identifying matching values. The system may also include additional logic to process the comparison results, such as generating control signals or routing data based on the outcomes. The use of a matrix structure allows for scalable and efficient parallel processing, reducing latency compared to sequential comparison methods. This approach is particularly useful in real-time systems where fast data analysis is critical, such as in network security, financial transactions, or scientific computing. The equality comparators ensure accurate identification of exact matches, which is essential for tasks requiring precise data alignment or validation.
10. The processor unit of claim 1 , wherein the processor unit is configured to position the characters of the target string that partially match the reference string at an end of the target string.
This invention relates to text processing systems that compare a target string to a reference string to identify partial matches. The problem addressed is efficiently organizing partially matching characters within the target string to improve readability or further processing. The system includes a processor unit that analyzes the target string to detect segments that partially match the reference string. When such matches are found, the processor unit rearranges the target string by moving the partially matching characters to the end of the string. This reorganization ensures that the remaining non-matching characters are grouped together at the beginning, making it easier to identify differences or perform subsequent operations. The processor unit may also include additional components, such as a memory unit to store the strings and a comparison module to perform the matching analysis. The system is particularly useful in applications like text editing, data validation, or pattern recognition where partial string alignment is required. By repositioning the matching segments, the invention simplifies the visualization and handling of mismatched content.
11. A method for searching within a target character string, using a processor unit comprising a plurality of vector registers each including vector elements, each vector element configured to contain a character, the method comprising: loading a reference string into a first register of the plurality of vector registers; loading a target string into a second register of the plurality of vector registers; performing, using an matrix of comparators, a comparison of characters of the reference string with characters of the target string; combining, with a plurality of logic gates, the results of comparators located along the respective diagonal of the matrix of comparators, the combining producing a bit vector indicating an item selected from the group consisting of: characters of the target string that fully match characters of the reference string and characters of the target string that partially match characters of the reference string; and generating, with logic, using the resulting bit vector, an indication of a substring of the target string that matches a portion of the reference string, the indication including the beginning of the substring and the length of the substring.
The invention relates to a method for efficiently searching within a target character string using vectorized processing. The method addresses the problem of slow string matching operations in traditional sequential processing by leveraging parallel processing capabilities of a processor unit with multiple vector registers. Each vector register contains vector elements, where each element can hold a character. The method involves loading a reference string into a first vector register and a target string into a second vector register. A matrix of comparators then performs parallel comparisons between characters of the reference string and the target string. The results of these comparisons, specifically those along the diagonal of the matrix, are combined using logic gates to produce a bit vector. This bit vector indicates either full or partial matches between characters of the target and reference strings. Further logic processes this bit vector to generate an indication of a substring within the target string that matches a portion of the reference string, including the starting position and length of the substring. This approach enables fast and efficient substring matching by utilizing parallel processing and vectorized operations.
12. The method of claim 11 , further comprising: identifying empty elements of the first register; generating a zero-bit vector having values indicating the identified empty elements and non-empty elements of the first register; and using the zero-bit vector for disregarding comparisons involving the identified empty elements.
This invention relates to data processing systems, specifically methods for optimizing comparison operations in register-based architectures. The problem addressed is the inefficiency in comparing data elements when some elements in a register are empty or invalid, leading to unnecessary computations and potential errors. The method involves processing a first register containing data elements, where some elements may be empty or invalid. The system identifies these empty elements and generates a zero-bit vector that maps the empty and non-empty elements of the first register. This zero-bit vector is then used to skip or disregard comparisons involving the identified empty elements, thereby improving computational efficiency and accuracy. The zero-bit vector acts as a mask, ensuring that only valid comparisons are performed. This approach is particularly useful in parallel processing environments where multiple comparisons are executed simultaneously, as it avoids wasted cycles on invalid data. The method can be applied in various computing systems, including those using vector registers or SIMD (Single Instruction, Multiple Data) architectures, to enhance performance and reliability. By dynamically filtering out empty elements, the system reduces overhead and prevents incorrect results from invalid comparisons.
13. The method of claim 11 , wherein bits of the resulting bit vector are ordered so that: a first bit of the resulting bit vector includes the results of comparators along the main diagonal of the matrix; and subsequent bits of the resulting bit vector include the results of comparators along respective subsequent diagonals adjacent to the main diagonal.
This invention relates to a method for processing a matrix of comparison results to generate an ordered bit vector. The method addresses the challenge of efficiently organizing comparison data from a matrix into a structured bit vector, which is useful in applications like sorting, searching, or parallel processing where diagonal-based comparisons are relevant. The method begins with a matrix of comparison results, where each element represents the outcome of a comparison between two elements. The matrix is processed to produce a bit vector, where each bit in the vector corresponds to the results of comparators along a specific diagonal of the matrix. The first bit of the resulting bit vector contains the results from the main diagonal of the matrix. Subsequent bits in the vector are ordered such that they include the results from diagonals adjacent to the main diagonal, progressing outward in a systematic manner. This ordering ensures that the bit vector preserves the spatial relationships of the original matrix, allowing for efficient retrieval and processing of comparison results. The method is particularly useful in systems where diagonal-based comparisons are performed, such as in certain sorting algorithms or parallel processing architectures. By organizing the comparison results in this structured way, the method enables faster access to relevant data and simplifies further processing steps. The invention improves upon existing techniques by providing a clear and efficient way to map matrix diagonals to a linear bit vector, enhancing computational efficiency and reducing complexity in downstream applications.
14. A computer program product for searching, within a target character string, for a reference character string of length “L,” using at least one processor unit comprising a plurality of vector registers each including a number “M” of n-bit vector elements, each vector element of the M n-bit vector elements configured to contain a binary-encoded character, the computer program product comprising at least one non-transitory computer-readable storage medium having program instructions embodied therewith, the program instructions executable by the at least one processor unit to cause the at least one processor unit to perform a method comprising: loading a reference string into a first register of the plurality of vector registers; loading a target string into a second register of the plurality of vector registers; performing, using an M×M matrix of comparators, a character-by-character comparison of characters of the reference string with characters of the target string; combining, with a plurality of logic gates, each logic gate of the plurality of logic gates associated with a respective diagonal of a triangular region of the matrix of comparators, the results of comparators located along the respective diagonal of the matrix of comparators, the combining producing a bit vector indicating at least one item selected from the group consisting of: characters of the target string that fully match characters of the reference string and characters of the target string that partially match characters of the reference string; and generating, with result generating logic, using the resulting bit vector, an indication of a substring of the target string that matches a fragment of the reference string, the indication including the beginning of the substring and the length of the substring.
This invention relates to a method for efficiently searching a target character string for a reference character string using vectorized processing. The problem addressed is the computational inefficiency of traditional string search algorithms, particularly for large datasets, by leveraging parallel processing capabilities of modern processors. The system uses a processor with vector registers, each containing multiple n-bit vector elements capable of storing binary-encoded characters. The reference string is loaded into a first vector register, and the target string is loaded into a second vector register. A matrix of comparators performs a character-by-character comparison between the reference and target strings in parallel. The results of these comparisons are processed using logic gates associated with diagonals of a triangular region within the matrix, producing a bit vector that indicates either full or partial matches between the strings. The bit vector is then used to generate an output indicating the beginning position and length of a substring in the target string that matches a fragment of the reference string. This approach enables rapid substring matching by exploiting parallel processing, reducing the time complexity of string search operations. The method is particularly useful in applications requiring high-speed text processing, such as search engines, bioinformatics, and natural language processing.
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August 18, 2020
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