Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A processing apparatus comprising: a plurality of arrays of resistive memory elements; a first and second configuration register, wherein at least one of the arrays is associated with the first and second configuration register, and the first and second configuration register is to specify a number of bits to be represented by the associated array, including the first configuration register to specify an activated row height of the associated array, and the second configuration register the specify a bit depth of the resistive memory elements of the associated array; and a controller to assign input data associated with a significance level to the associated array based on the significance level, wherein the controller is to assign input data associated with a higher significance level to an array representing a first number of bits, and the controller is further to assign input data associated with a lower significance level to an array representing a second number of bits, wherein the first number of bits is smaller than the second number of bits, and wherein the controller is to control at least one of the activated row height and the bit depth of the associated array based on the significance level of data assigned thereto.
This invention relates to a processing apparatus designed to optimize data storage and processing in resistive memory arrays by dynamically adjusting the bit representation based on data significance. The apparatus includes multiple arrays of resistive memory elements, each associated with two configuration registers. The first configuration register specifies the activated row height of the array, while the second configuration register defines the bit depth of the resistive memory elements within that array. A controller assigns input data to these arrays based on their significance level, prioritizing higher significance data to arrays configured for fewer bits and lower significance data to arrays configured for more bits. The controller dynamically adjusts the activated row height and bit depth of each array according to the significance of the data stored therein. This approach improves efficiency by allocating more precise storage to critical data while using less precise storage for less important data, optimizing both memory usage and processing performance. The system leverages the configurable nature of resistive memory to balance accuracy and resource utilization dynamically.
2. The processing apparatus according to claim 1 in which the input data comprises a plurality of input data portions, each input data portion comprising a bit slice of a data input, and the controller is to assign the input data portions to a plurality of different arrays of the plurality of arrays based on a significance level associated with each input data portion, the processing apparatus further comprising a data output module to receive at least one output bit from the plurality of different arrays and to combine the output bits to provide a combined output comprising a plurality of output bits having a bit sequence corresponding to the data input.
This invention relates to a processing apparatus for handling input data comprising multiple bit slices, where each bit slice has a significance level. The apparatus includes a controller that assigns these bit slices to different arrays within a plurality of arrays based on their significance levels. The apparatus also includes a data output module that receives output bits from the different arrays and combines them to produce a combined output. The combined output is a sequence of bits that corresponds to the original data input. The apparatus is designed to efficiently process data by distributing bit slices across multiple arrays, optimizing performance based on the significance of each bit slice. This approach allows for parallel processing and improved data handling in systems where bit significance affects computational efficiency. The invention is particularly useful in applications requiring high-speed data processing, such as digital signal processing, cryptography, or machine learning, where bit-level operations are critical. The apparatus ensures that higher significance bits are processed in a manner that prioritizes accuracy and speed, while lower significance bits may be handled with less critical resources. This method enhances overall system performance by leveraging the significance-based distribution of data across multiple arrays.
3. The processing apparatus according to claim 2 which further comprises a bit error module to estimate a bit error rate of at least one output bit from at least one array of the plurality of arrays, wherein the data output module is to approximate bits having a bit error rate above a threshold bit error rate from the combined output to a predetermined value.
This invention relates to processing apparatuses for handling data from multiple arrays, particularly focusing on error correction and data output. The apparatus includes a data output module that combines outputs from a plurality of arrays to generate a combined output. The apparatus further includes a bit error module that estimates the bit error rate of at least one output bit from at least one array. If the bit error rate exceeds a predefined threshold, the data output module approximates those bits in the combined output to a predetermined value, effectively correcting errors by replacing unreliable data with a fixed value. This approach improves data integrity by mitigating the impact of high-error-rate bits, ensuring more reliable output. The system is designed to enhance performance in applications where data accuracy is critical, such as memory storage or signal processing, by dynamically adjusting output based on error rate thresholds. The invention addresses the challenge of maintaining data reliability in systems where individual arrays may produce variable error rates, providing a robust solution for error handling in multi-array processing environments.
4. The processing apparatus according to claim 2 , wherein an output bit depth of the plurality of output bits is equal to a target operand output width specified by a processing operation being carried out by the processing apparatus.
This invention relates to a processing apparatus designed to optimize data processing efficiency by dynamically adjusting the bit depth of output data based on the requirements of the specified processing operation. The apparatus includes a processing unit that executes operations on input data, where the input data is represented by a plurality of input bits. The processing unit generates output data as a plurality of output bits, and the bit depth of these output bits is configurable. The apparatus further includes a control unit that determines the target operand output width required by the processing operation being executed. The control unit then configures the processing unit to ensure that the output bit depth matches this target operand output width. This dynamic adjustment prevents unnecessary bit expansion or truncation, improving processing efficiency and reducing resource usage. The apparatus may also include a storage unit to hold intermediate or final results, and the control unit may manage data flow between the processing unit and storage unit to maintain optimal bit depth throughout the operation. This approach is particularly useful in systems where different operations require different precision levels, such as in digital signal processing or machine learning workloads.
5. The processing apparatus according to claim 1 , wherein the input data is associated with an application type and at least one of the higher or lower significance level is based at least in part on the application type.
A processing apparatus is designed to handle input data by assigning significance levels to different portions of the data, which can then be used to prioritize processing tasks. The apparatus includes a data analyzer that evaluates the input data to determine its structure and content, identifying segments that may require different levels of processing priority. A significance level assigner then categorizes these segments into higher or lower significance levels based on predefined criteria, such as the importance of the data within a specific context. A processing controller then manages the execution of tasks based on these assigned significance levels, ensuring that higher-priority segments are processed first or with greater resources. In an enhanced version of this apparatus, the input data is associated with an application type, and the determination of higher or lower significance levels is influenced by this application type. For example, in a financial application, transaction data may be assigned a higher significance level compared to metadata, while in a media application, key frames in a video stream may be prioritized over less critical frames. This allows the apparatus to adapt its processing strategy dynamically based on the specific requirements of the application, improving efficiency and performance. The apparatus can be integrated into various systems, such as real-time data processing platforms, where prioritization of data segments is crucial for optimal performance.
6. The processing apparatus according to claim 1 , wherein a portion of the input data is associated with a significance level based on a content of the input data.
This invention relates to processing apparatuses designed to handle input data with varying levels of significance. The apparatus identifies and processes portions of the input data based on their significance, which is determined by analyzing the content of the data. The significance level may influence how the data is prioritized, filtered, or otherwise managed during processing. The apparatus may include components for receiving input data, analyzing its content to assign significance levels, and applying processing rules based on those levels. This approach ensures that critical or high-priority data is handled appropriately, improving efficiency and accuracy in data processing tasks. The invention is particularly useful in applications where data varies in importance, such as real-time analytics, decision-making systems, or content filtering. By dynamically adjusting processing based on significance, the apparatus optimizes resource allocation and enhances overall system performance.
7. A processing apparatus comprising: a plurality of arrays of resistive memory elements; at least one configuration register, wherein at least one of the arrays is associated with the at least one configuration register, and the at least one configuration register is to specify a number of bits to be represented by the associated array; a controller to assign input data portions of input data to different arrays of the plurality of arrays based on a significance level associated with each input data portion, wherein each data portion comprises a bit slice of the input data and wherein the controller is to assign an input data portion associated with a higher significance level to an array representing a first number of bits, and the controller is further to assign an input data portion associated with a lower significance level to an array representing a second number of bits, wherein the first number of bits is smaller than the second number of bits; and a data output module to receive at least one output bit from each of the different arrays and to combine the output bits to provide a combined output comprising a plurality of output bits having a bit sequence corresponding to the data input.
This invention relates to a processing apparatus for handling input data using resistive memory elements, addressing the challenge of efficiently processing data with varying significance levels. The apparatus includes multiple arrays of resistive memory elements, each capable of storing and processing data. At least one configuration register is associated with one or more arrays, specifying the number of bits each array represents. A controller assigns portions of input data to different arrays based on their significance levels. Each data portion is a bit slice of the input data, and the controller ensures that higher significance data portions are assigned to arrays representing fewer bits, while lower significance data portions are assigned to arrays representing more bits. This approach optimizes storage and processing efficiency by allocating resources proportionally to the importance of the data. The data output module collects output bits from the different arrays and combines them into a final output that reconstructs the original input data sequence. The system enhances performance by dynamically adjusting bit representation based on data significance, improving accuracy and resource utilization in resistive memory-based processing.
8. The processing apparatus of claim 7 , further comprising a bit error module to estimate a bit error rate of at least one output bit from at least one array of the plurality of arrays, wherein the data output module is to approximate bits having a bit error rate above a threshold bit error rate from the combined output to a predetermined value.
This invention relates to processing apparatuses for handling data from multiple arrays, particularly in systems where data integrity is critical. The apparatus includes a data output module that combines output bits from a plurality of arrays to generate a combined output. The system addresses the problem of bit errors in data processing, where individual arrays may produce corrupted or unreliable bits due to noise, interference, or other factors. To mitigate this, the apparatus includes a bit error module that estimates the bit error rate (BER) of at least one output bit from the arrays. If the BER exceeds a predefined threshold, the data output module approximates those bits to a predetermined value (e.g., 0 or 1) to improve data reliability. This ensures that high-error bits do not propagate through the system, enhancing overall data accuracy. The invention is particularly useful in applications where multiple data sources are aggregated, such as in memory systems, communication networks, or sensor arrays, where error correction is essential for maintaining performance and reliability. The apparatus dynamically adjusts output bits based on error rates, providing a robust solution for error-prone data environments.
9. A method comprising: configuring, by at least one configuration register associated with an array of a plurality of arrays of resistive memory elements, a number of bits to be represented by the associated array; assigning input data portions of input data to different arrays of the plurality of arrays based on a significance level associated with each input data portion, wherein each data portion comprises a bit slice of the input data and wherein assigning the input data portions includes assigning an input data portion associated with a higher significance level to an array representing a first number of bits, and assigning an input data portion associated with a lower significance level to an array representing a second number of bits, wherein the first number of bits is smaller than the second number of bits; receiving, by a data output module, at least one output bit from each of the different arrays; and combining the output bits to provide a combined output comprising a plurality of output bits having a bit sequence corresponding to the data input.
This invention relates to resistive memory systems and addresses the challenge of efficiently processing input data with varying significance levels in a memory array. The method involves configuring a configuration register associated with an array of resistive memory elements to determine the number of bits each array can represent. Input data is divided into portions, each representing a bit slice of the original data, and assigned to different arrays based on their significance. Higher significance data portions are assigned to arrays configured to represent fewer bits, while lower significance data portions are assigned to arrays configured to represent more bits. This ensures that more critical data is processed with higher precision. A data output module collects at least one output bit from each array and combines them to reconstruct the original bit sequence. The approach optimizes memory usage and processing efficiency by dynamically allocating bit representation based on data significance, improving accuracy for critical data while reducing resource consumption for less significant data. The method is particularly useful in applications requiring adaptive precision, such as machine learning or signal processing, where different data portions contribute differently to the overall result.
10. The method according to claim 9 , wherein configuring the number of bits to be represented by the associated array further comprises configuring, according to the significance level of the input data to be processed, at least one of (i) a number of input rows and (ii) a bit depth of resistive memory elements of the associated array.
This invention relates to optimizing data processing in resistive memory arrays, particularly for handling input data with varying significance levels. The method involves configuring the number of bits represented by a resistive memory array based on the significance of the input data. This includes adjusting either the number of input rows or the bit depth of the resistive memory elements within the array. By dynamically configuring these parameters, the system can efficiently process data with different levels of importance, improving computational accuracy and resource utilization. The resistive memory elements are used to store and process data in a non-volatile manner, leveraging their ability to represent multiple bit states. The method ensures that higher significance data is processed with greater precision, while lower significance data can be handled with reduced resource consumption. This approach enhances the flexibility and efficiency of resistive memory-based computing systems, making them suitable for applications requiring adaptive data processing.
11. The method according to claim 9 , further comprising: processing data with each of the different arrays to provide the at least one output bit from each of the different arrays.
This invention relates to data processing systems that use multiple arrays to enhance computational efficiency and reliability. The problem addressed is improving the performance and fault tolerance of data processing operations by leveraging parallel processing across different arrays. The method involves distributing data processing tasks across multiple arrays, where each array independently processes the same or related data to generate at least one output bit. This parallel processing approach allows for redundancy, error correction, and increased throughput by utilizing the combined computational power of the arrays. The arrays may operate in parallel or sequentially, depending on the specific implementation, to ensure accurate and efficient data processing. The method is particularly useful in applications requiring high reliability, such as error-critical systems or environments where data integrity is paramount. By processing data with each array to produce output bits, the system can cross-validate results, detect errors, and improve overall system robustness. The invention is applicable in fields such as digital signal processing, cryptography, and fault-tolerant computing, where parallel processing and redundancy are essential for performance and reliability.
12. The method according to claim 9 where the input data is associated with an application type and at least one of the higher or lower significance level is based at least in part on the application type.
This invention relates to data processing systems that prioritize input data based on its significance level, particularly in applications where different types of data require varying levels of processing urgency. The problem addressed is the inefficient handling of input data in systems where all data is processed uniformly, leading to delays in critical operations or unnecessary resource consumption for low-priority tasks. The method involves analyzing input data to determine its significance level, which dictates how quickly or thoroughly it should be processed. The significance level is dynamically adjusted based on the application type associated with the input data. For example, in a healthcare monitoring system, patient vital signs data may be assigned a higher significance level than administrative records, ensuring timely processing of critical health information. The system may also use predefined rules or machine learning models to assess significance, allowing for adaptive prioritization. By tailoring the processing priority to the application type, the system optimizes resource allocation and improves overall efficiency. This approach is particularly useful in environments where different data types have distinct urgency requirements, such as industrial automation, financial transactions, or real-time analytics. The method ensures that high-priority data is processed promptly while lower-priority data receives appropriate but less immediate attention, balancing system performance and resource utilization.
13. The method according to claim 9 , further comprising determining a significance level for portions of the input data based on a content of the input data.
This invention relates to data processing systems that analyze input data to determine significance levels for different portions of the data. The problem addressed is the need to identify and prioritize meaningful segments within large datasets, which is particularly useful in applications like natural language processing, signal analysis, or machine learning where certain data portions carry more weight than others. The method involves processing input data to extract features or patterns, then evaluating these features to assign a significance level to different portions of the data. The significance level is determined based on the content of the input data, meaning the analysis considers the actual information within the data rather than just its structure. For example, in text analysis, certain words or phrases may be flagged as more significant based on their context, frequency, or semantic relevance. In signal processing, specific frequency components or time intervals may be identified as more important for further analysis. The method may also include preprocessing steps to prepare the input data for significance analysis, such as filtering, normalization, or segmentation. The significance levels can then be used to guide subsequent processing steps, such as feature selection, data compression, or decision-making algorithms. This approach improves efficiency by focusing computational resources on the most relevant data portions, leading to more accurate and faster results in applications like predictive modeling, anomaly detection, or content summarization.
14. The method of claim 9 , further comprising estimating a bit error rate of at least one output bit from at least one array of the plurality of arrays.
This invention relates to error detection in memory systems, specifically for estimating bit error rates in multi-array memory configurations. The method involves analyzing output bits from multiple memory arrays to assess data integrity. A key feature is the estimation of the bit error rate (BER) for at least one output bit from at least one array within the system. This process helps identify and quantify errors in stored or retrieved data, improving reliability in memory operations. The technique may involve comparing expected and actual bit values, statistical analysis of error patterns, or other error detection mechanisms. By monitoring BER across arrays, the system can detect degradation, correct errors, or trigger maintenance actions. This approach is particularly useful in high-density or high-reliability memory systems where error rates must be minimized. The method may integrate with existing error correction or detection schemes to enhance overall system robustness. The focus is on accurately estimating BER to ensure data integrity in memory operations.
15. The method of claim 14 , further comprising dropping, by the data output module, output bits having a bit error rate above a threshold bit error rate from the combined output.
A method for processing data in a communication system involves receiving input data from multiple sources, such as sensors or communication channels, and combining the data to generate a combined output. The method includes analyzing the combined output to identify errors, such as bit errors, and correcting those errors to improve data accuracy. The method further includes filtering the combined output by removing output bits that have a bit error rate exceeding a predefined threshold. This ensures that only high-quality data is retained for further processing or transmission. The method may also involve adjusting the threshold bit error rate dynamically based on system conditions or performance requirements. The technique is particularly useful in systems where data integrity is critical, such as in wireless communication, sensor networks, or error-prone data transmission environments. By selectively discarding low-quality data, the method enhances overall system reliability and reduces the impact of corrupted data on downstream applications.
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August 25, 2020
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