Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A system, comprising: a memory component including a plurality of memory cells; and a processing device, operatively coupled to the memory device, to: determine a first vector having a first magnitude and a first phase angle relative to a reference axis, the first vector corresponding to a difference between an error value for a current processing level for processing data and an error value for a first offset processing level, determine a second vector having a second magnitude and a second phase angle relative to the reference axis, the second vector corresponding to a difference between the error value for the current processing level and an error value for a second offset processing level, wherein the first offset processing level is different from the second offset processing level, generate an estimated processing level offset based on at least one of a difference between the first magnitude and the second magnitude or a difference between the first phase angle and the second phase angle, and generate an updated processing level based on the estimated processing level offset, the updated processing level to replace the current processing level, wherein the current processing level and the updated processing level relate to processing the data for a subset of the plurality of memory cells.
This invention relates to a system for optimizing data processing in memory devices, particularly for adjusting processing levels to minimize errors in memory cell operations. The system includes a memory component with multiple memory cells and a processing device connected to the memory. The processing device determines a first vector representing the difference in error values between a current processing level and a first offset processing level, where the vector has a magnitude and phase angle relative to a reference axis. Similarly, it determines a second vector for a second offset processing level, distinct from the first. The system then calculates an estimated processing level offset by comparing either the magnitudes or phase angles of these vectors. Using this offset, the system generates an updated processing level to replace the current one, improving data processing accuracy for a subset of memory cells. The approach leverages vector analysis to dynamically adjust processing parameters, reducing errors in memory operations. This method is particularly useful in memory systems where precise data handling is critical, such as in storage or computing applications.
2. The system of claim 1 , wherein the generation of the estimated processing level offset includes estimating a shift in a process level value of the current processing level based on a difference between at least one component of the first magnitude or at least one component of the second magnitude.
The system relates to semiconductor manufacturing, specifically to process control in lithography or etching systems where precise control of processing levels is critical. The problem addressed is maintaining consistent processing levels despite variations in process conditions, such as fluctuations in etch rates or lithography exposure doses, which can lead to defects or yield loss. The system estimates a processing level offset to adjust the current processing level based on measured magnitudes. These magnitudes may include parameters like etch rates, exposure doses, or other process variables that influence the processing level. The system compares at least one component of a first magnitude (e.g., a baseline or reference value) with at least one component of a second magnitude (e.g., a real-time or measured value) to determine a difference. This difference is used to estimate a shift in the process level value, which is then applied as an offset to correct or adjust the current processing level. The correction ensures that the process remains within acceptable tolerances, improving uniformity and yield. The system may also include feedback mechanisms to continuously monitor and adjust the processing level, ensuring real-time compensation for process variations. This approach is particularly useful in advanced semiconductor manufacturing where tight control of process parameters is essential for device performance and reliability.
3. The system of claim 2 , wherein the shift in the process level value is further based on a characteristic of a valley distribution associated with the current processing level.
A system for semiconductor manufacturing monitors and adjusts process levels during fabrication to improve yield and consistency. The system tracks variations in process parameters, such as etch depth or film thickness, and detects deviations from target values. To compensate for these deviations, the system adjusts the process level by shifting it based on a characteristic of a valley distribution associated with the current processing level. The valley distribution represents the statistical spread of process outcomes, and its characteristics—such as depth, width, or skewness—help determine the optimal shift needed to correct deviations. This adjustment ensures that subsequent processing steps align more closely with desired specifications, reducing defects and improving uniformity. The system may also incorporate feedback from previous adjustments to refine future corrections, enhancing overall process control. By dynamically adjusting process levels based on real-time data and statistical distributions, the system improves manufacturing precision and yield in semiconductor fabrication.
4. The system of claim 2 , wherein the determination of the first vector, the determination of the second vector, the generation of the estimated processing level offset, the generation of the updated processing level, and replacement of the current processing level with the updated processing level is processed iteratively until at least one of, the difference between the first magnitude and the second magnitude is within a first predetermined value, the difference between the first phase and a negative of the second phase with respect to the reference axis is within a second predetermined value, wherein the reference axis corresponds to the updated processing level, or a dither condition is reached for the updated processing level.
This invention relates to a system for iteratively adjusting a processing level in a signal processing application, such as audio or communication systems, to optimize performance. The system addresses the challenge of dynamically aligning signal characteristics, such as magnitude and phase, to a desired processing level while minimizing deviations and ensuring stability. The system determines a first vector representing a current signal state, including its magnitude and phase relative to a reference axis. A second vector is determined for a target signal state, also including magnitude and phase. An estimated processing level offset is generated based on the difference between these vectors, and an updated processing level is derived by applying this offset to the current processing level. The system then replaces the current processing level with this updated value. This process is repeated iteratively until one of three conditions is met: the difference between the magnitudes of the first and second vectors falls within a predefined tolerance, the phase difference between the first vector and the negative of the second vector (relative to the updated processing level) is within another predefined tolerance, or a dither condition is reached, indicating minimal further adjustments are needed. The iterative approach ensures precise alignment of signal characteristics while avoiding excessive processing or instability. The reference axis dynamically adjusts with each update, ensuring accurate phase alignment throughout the process.
5. The system of claim 4 , wherein the updated processing level is an output of a convergence function with the estimated processing level offset as an input to the convergence function, the convergence function determining a rate of convergence for the iterative processing, and wherein a gain for the convergence function is dependent on a type of memory cell in the subset of the plurality of memory cells.
This invention relates to memory systems, specifically to techniques for adjusting processing levels in memory cells during iterative processing. The problem addressed is optimizing the convergence rate of iterative processing in memory systems, particularly when dealing with different types of memory cells that may require distinct processing approaches. The system includes a memory controller configured to perform iterative processing on a subset of memory cells. During this process, the controller estimates a processing level offset for the subset of cells. This offset is then used as an input to a convergence function, which determines the updated processing level for the next iteration. The convergence function controls the rate at which the processing converges, ensuring efficient and accurate data recovery or programming. The gain of the convergence function is adjusted based on the type of memory cell being processed, allowing the system to adapt to different memory technologies, such as NAND flash, DRAM, or other non-volatile memory types. This adaptive approach improves processing efficiency and reliability by tailoring the convergence behavior to the specific characteristics of the memory cells involved. The system may also include mechanisms to track convergence progress and adjust parameters dynamically to optimize performance.
6. The system of claim 1 , wherein the plurality of memory cells is arranged in a plurality of memory pages, and wherein the subset comprises one of the plurality of memory pages.
A memory system includes a plurality of memory cells arranged in multiple memory pages, where each memory page contains a subset of the memory cells. The system is designed to manage data storage and retrieval operations efficiently, particularly in non-volatile memory devices such as flash memory. The arrangement of memory cells into pages allows for optimized read and write operations, as data is typically accessed or modified in page-sized blocks rather than at the level of individual cells. This structure improves performance by reducing the overhead associated with addressing and managing large numbers of individual memory cells. The system may also include error correction mechanisms, wear-leveling algorithms, or other techniques to enhance reliability and longevity. The use of memory pages simplifies data management by grouping cells into logical units, which can be erased, programmed, or read as a single entity. This approach is particularly useful in solid-state storage devices where efficient data handling is critical for performance and endurance. The system may further include controllers or firmware to handle page-level operations, ensuring consistent and reliable access to stored data.
7. The system of claim 1 , wherein the current processing level, the first offset processing level, the second offset processing level, and the updated processing level are threshold voltages corresponding to read levels.
The invention relates to a system for managing read operations in non-volatile memory, particularly addressing the challenge of accurately determining threshold voltages for read levels to improve data reliability. The system dynamically adjusts read levels based on changes in memory cell characteristics over time, such as wear or environmental factors, to maintain accurate data retrieval. The system includes multiple processing levels defined as threshold voltages used during read operations. These include a current processing level, a first offset processing level, and a second offset processing level, which are adjusted to account for variations in memory cell behavior. The system also updates these levels to an updated processing level based on detected changes, ensuring that read operations remain precise even as memory cells degrade or environmental conditions fluctuate. The system may involve comparing read results from different processing levels to identify optimal read thresholds, adjusting these levels in response to errors or performance metrics, and applying the updated levels to subsequent read operations. This dynamic adjustment helps mitigate errors caused by shifts in threshold voltages, improving the reliability and longevity of non-volatile memory storage. The invention is particularly useful in flash memory and other storage technologies where read level accuracy is critical for data integrity.
8. A method, comprising: sampling center, first, and second error values for a current processing level, a first offset processing level, and a second offset processing level, respectively, wherein the first offset processing level is different from the second offset processing level; determining a first vector having a first magnitude and a first phase angle relative to a reference axis, the first vector corresponding to a difference between the center and first error values; determining a second vector having a second magnitude and a second phase angle relative to the reference axis, the second vector corresponding to a difference between the center and second error values; generating an estimated processing level offset based on at least one of a difference between the first magnitude and the second magnitude or a difference between the first phase angle and the second phase angle; and generating an updated processing level based on the estimated processing level offset, the updated processing level to replace the current processing level, wherein the current processing level and the updated processing level relate to processing data corresponding to a subset of a plurality of memory cells of a memory component.
This invention relates to error correction and processing level adjustment in memory systems, particularly for managing data stored in subsets of memory cells. The problem addressed involves inaccuracies in processing levels due to variations in error values across different memory cell subsets, which can degrade data integrity and performance. The method samples error values at three distinct processing levels: a current level, a first offset level, and a second offset level, where the offsets differ. From these samples, two vectors are derived. The first vector represents the difference between the center (current) and first offset error values, characterized by a magnitude and phase angle relative to a reference axis. The second vector represents the difference between the center and second offset error values, similarly defined by magnitude and phase. The method then estimates a processing level offset by comparing either the magnitudes or phase angles of these vectors. This offset is used to generate an updated processing level, which replaces the current level to improve accuracy. The technique applies to data processing for subsets of memory cells in a memory component, enhancing error correction and data reliability.
9. The method of claim 8 , wherein the generating of the estimated processing level offset includes estimating a shift in a process level value of the current processing level based on a difference between at least one component of the first magnitude or at least one component of the second magnitude.
This invention relates to semiconductor manufacturing, specifically to methods for adjusting processing levels in lithography or etching processes to compensate for variations in critical dimensions (CDs). The problem addressed is maintaining consistent CD uniformity across wafers by dynamically adjusting processing parameters based on measured variations in feature dimensions. The method involves analyzing first and second magnitude values representing measured dimensions of features on a wafer. These magnitudes may include components such as horizontal, vertical, or other directional dimensions. The method estimates a shift in the process level value of the current processing level by comparing at least one component of the first magnitude with at least one component of the second magnitude. This shift is used to generate an estimated processing level offset, which is then applied to adjust subsequent processing steps. The adjustment compensates for deviations in feature dimensions, ensuring tighter control over CD uniformity. The method may also include generating a first magnitude value from a first set of measured dimensions and a second magnitude value from a second set of measured dimensions, where these sets may correspond to different regions of the wafer or different types of features. The estimated processing level offset is derived from the difference between these magnitudes, allowing for fine-tuned adjustments to processing parameters such as exposure dose, etch time, or other process variables. This approach improves yield and reduces defects by dynamically correcting for variations in the manufacturing process.
10. The method of claim 9 , wherein the shift in the process level value is further based on a characteristic of a valley distribution associated with the current processing level.
A method for adjusting process levels in semiconductor manufacturing involves analyzing a valley distribution associated with the current processing level to determine a shift in the process level value. The valley distribution represents variations in process parameters, such as critical dimensions or electrical characteristics, across a wafer or batch of wafers. By evaluating this distribution, the method identifies optimal adjustments to the process level to improve yield or performance. The shift is calculated based on statistical properties of the valley distribution, such as its depth, width, or position, ensuring that the process remains within acceptable limits while minimizing defects. This approach enhances process control by dynamically adapting to variations in the manufacturing environment, reducing waste and improving consistency in semiconductor fabrication. The method integrates with existing process monitoring systems to provide real-time feedback and adjustments, ensuring high precision in semiconductor production.
11. The method of claim 9 , further comprising: processing iteratively the determining of the first vector, the determining of the second vector, the generating of the estimated processing level offset, the generating of the updated processing level, and replacing of the current processing level with the updated processing level until at least one of, the difference between the first magnitude and the second magnitude is within a first predetermined value, the difference between the first phase and a negative of the second phase with respect to the reference axis is within a second predetermined value, wherein the reference axis corresponds to the updated processing level, or a dither condition is reached for the updated processing level.
This invention relates to iterative signal processing methods for adjusting processing levels in systems where signal magnitude and phase alignment are critical. The method addresses the challenge of dynamically optimizing processing levels to minimize discrepancies between a first vector and a second vector, which may represent signals or system states. The first vector is determined based on a current processing level, while the second vector is derived from a reference or target signal. The method generates an estimated processing level offset by comparing the magnitudes and phases of these vectors. The offset is then used to update the processing level, replacing the current level with the updated one. This process is repeated iteratively until one of three termination conditions is met: the difference between the magnitudes of the first and second vectors falls within a predefined threshold, the phase difference between the first vector and the negative of the second vector (relative to a reference axis aligned with the updated processing level) is within another predefined threshold, or a dither condition is reached, indicating minimal further improvement. The iterative approach ensures precise alignment of signal characteristics, enhancing system performance in applications such as communication systems, control loops, or signal synchronization.
12. The method of claim 11 , further comprising: determining a rate of convergence for the iterative generation based on a type of memory cell in the subset of the plurality of memory cells.
This invention relates to memory cell programming in non-volatile memory systems, specifically addressing challenges in optimizing programming algorithms for different memory cell types. The method involves iteratively generating programming parameters for a subset of memory cells, where the programming parameters are adjusted based on feedback from previous programming cycles. The key improvement is determining a rate of convergence for the iterative generation process based on the specific type of memory cell being programmed. Different memory cell types, such as single-level cells (SLC), multi-level cells (MLC), or triple-level cells (TLC), exhibit distinct electrical characteristics and programming behaviors. By tailoring the convergence rate to the cell type, the method ensures efficient and accurate programming while minimizing over-programming or under-programming. The iterative process may involve adjusting voltage levels, pulse durations, or other programming parameters until the target threshold voltage distribution is achieved. This approach improves programming speed, reliability, and endurance by dynamically adapting to the unique requirements of each memory cell type. The method is particularly useful in flash memory systems where varying cell types are present, ensuring consistent performance across different memory configurations.
13. The method of claim 9 , wherein the plurality of memory cells is arranged in a plurality of memory pages, and wherein the subset comprises one of the plurality of memory pages.
This invention relates to memory systems, specifically methods for managing memory cells in a storage device. The problem addressed is efficient data handling in memory arrays, particularly when dealing with subsets of memory cells organized into pages. The method involves selecting a subset of memory cells from a larger array, where the subset is defined as a single memory page. Memory pages are predefined groupings of cells that facilitate organized data storage and retrieval. The method ensures that operations such as reading, writing, or erasing are performed on entire pages rather than individual cells, improving efficiency and reducing overhead. By aligning operations with page boundaries, the system minimizes fragmentation and optimizes performance. The approach is particularly useful in non-volatile memory systems like flash storage, where page-level operations are standard. The method may also include additional steps such as error detection or correction, wear leveling, or garbage collection, which are common in memory management. The invention aims to enhance data integrity and system longevity by leveraging structured page-based access.
14. The method of claim 8 , wherein the current processing level, the first offset processing level, the second offset processing level, and the updated processing level are threshold voltages corresponding to read levels.
A method for adjusting read threshold voltages in a memory storage system addresses the challenge of accurately retrieving data from memory cells that degrade over time. The method involves dynamically modifying read threshold voltages to compensate for shifts in cell characteristics, ensuring reliable data retrieval. The process begins by determining a current processing level, which is a threshold voltage used for reading data from memory cells. Two offset processing levels are then calculated, representing adjusted threshold voltages that account for variations in cell behavior. These offsets are derived based on factors such as cell wear, temperature, or other environmental conditions. The method further updates the processing level to an optimized value, which is a refined threshold voltage that improves read accuracy. This updated level is determined by analyzing the relationship between the current processing level and the offset levels, ensuring that the read operation aligns with the actual data stored in the cells. The technique helps mitigate errors caused by threshold voltage drift, enhancing the longevity and reliability of memory storage devices. By dynamically adjusting read thresholds, the method ensures consistent data retrieval performance even as memory cells degrade.
15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to: determine a first vector having a first magnitude and a first phase angle relative to a reference axis, the first vector corresponding to a difference between an error value for a current processing level for processing data and an error value for a first offset processing level; determine a second vector having a second magnitude and a second phase angle relative to a reference axis, the second vector corresponding to a difference between the error value for the current processing level and an error value for a second offset processing level for processing the data, wherein the first offset processing level is different from the second offset processing level; generate an estimated processing level offset based on at least one of a difference between the first magnitude and the second magnitude or a difference between the first phase angle and the second phase angle; and generate an updated processing level based on the estimated processing level offset, the updated processing level to replace the current processing level, wherein the current processing level and the updated processing level relate to processing the data corresponding to a subset of a plurality of memory cells of a memory component.
This invention relates to optimizing data processing levels in memory systems, particularly for subsets of memory cells in a memory component. The problem addressed is the need to dynamically adjust processing levels to minimize errors during data retrieval or storage, improving reliability and performance. The system determines two vectors representing error differences between a current processing level and two distinct offset processing levels. The first vector corresponds to the difference between the error at the current level and the error at a first offset level, while the second vector corresponds to the difference between the current error and the error at a second offset level. Each vector has a magnitude and phase angle relative to a reference axis. The system then estimates an optimal processing level offset by analyzing the differences in magnitudes or phase angles of these vectors. This estimated offset is used to generate an updated processing level, which replaces the current level for processing data associated with a subset of memory cells. The approach leverages vector-based error analysis to refine processing levels, enhancing accuracy and efficiency in memory operations.
16. The non-transitory computer-readable storage medium of claim 15 , wherein the generating of the estimated processing level offset includes estimating a shift in a process level value of the current processing level based on a difference between at least one component of the first magnitude or at least one component of the second magnitude.
This invention relates to semiconductor manufacturing, specifically to adjusting processing levels in lithography or etching processes to compensate for variations in wafer processing. The problem addressed is maintaining consistent process uniformity despite variations in wafer characteristics or environmental conditions, which can lead to defects or yield loss. The invention involves a method for estimating and applying a processing level offset to correct deviations in a semiconductor fabrication process. A first magnitude representing a measured process level of a wafer is obtained, and a second magnitude representing a target or reference process level is determined. The system generates an estimated processing level offset by analyzing differences between components of these magnitudes, such as comparing specific process parameters like exposure dose, etch rate, or film thickness. The offset is then applied to adjust the current processing level, ensuring the wafer is processed at the correct level despite variations. The invention also includes a non-transitory computer-readable storage medium containing instructions for performing these steps. The offset estimation involves calculating a shift in the process level value based on discrepancies between components of the first and second magnitudes, allowing for precise corrections. This approach improves process control, reduces defects, and enhances yield in semiconductor manufacturing.
17. The non-transitory computer-readable storage medium of claim 15 , wherein the shift in the process level value is further based on a characteristic of a valley distribution associated with the current processing level.
This invention relates to semiconductor manufacturing, specifically to adjusting process levels in fabrication processes to improve yield and performance. The problem addressed is the variability in semiconductor device performance due to process variations, which can lead to defects or suboptimal performance. The invention provides a method to dynamically adjust process levels during fabrication by analyzing statistical distributions of process parameters, particularly focusing on the characteristics of a valley distribution associated with the current processing level. The valley distribution represents a range of process parameter values where device performance is most stable. By incorporating this distribution into process level adjustments, the method ensures that adjustments are made in a way that maintains or improves device performance while minimizing variability. The system uses historical data and real-time measurements to refine the process level shifts, ensuring that adjustments are data-driven and adaptive to changing conditions. This approach helps in reducing defects, improving yield, and enhancing the overall reliability of semiconductor devices. The invention is particularly useful in advanced semiconductor manufacturing where tight control over process parameters is critical.
18. The non-transitory computer-readable storage medium of claim 15 , further causing the processing device to: processing iteratively the determining of the first vector, the determining of the second vector, the generating of the estimated processing level offset, the generating of the updated processing level, and replacing of the current processing level with the updated processing level until at least one of, the difference between the first magnitude and the second magnitude is within a first predetermined value, the difference between the first phase and a negative of the second phase with respect to the reference axis is within a second predetermined value, wherein the reference axis corresponds to the updated processing level, or a dither condition is reached for the updated processing level.
This invention relates to signal processing, specifically iterative adjustment of processing levels in systems where precise magnitude and phase alignment are critical, such as in communication systems or control loops. The problem addressed is achieving stable and accurate processing levels by dynamically compensating for deviations in magnitude and phase between two vectors derived from a signal. The solution involves an iterative process that continuously refines the processing level until convergence criteria are met. The method processes a signal to determine a first vector representing a current state and a second vector representing a desired or corrected state. A processing level offset is generated based on the difference between the magnitudes and phases of these vectors. The current processing level is then updated by applying this offset. This iterative process repeats, recalculating the vectors, offset, and updated processing level, until one of three conditions is satisfied: the magnitude difference falls within a predefined tolerance, the phase difference (relative to a reference axis aligned with the updated processing level) falls within another predefined tolerance, or a dither condition (a state where further adjustments cause negligible improvement) is detected. The reference axis dynamically adjusts with each update to ensure phase alignment accuracy. This approach ensures precise and stable processing levels, minimizing errors in systems sensitive to magnitude and phase discrepancies.
19. The non-transitory computer-readable storage medium of claim 18 , further causing the processing device to: determine a rate of convergence for the iterative generation based on a type of memory cell in the subset of the plurality of memory cells.
The invention relates to optimizing memory cell programming in non-volatile memory systems, particularly for improving the efficiency and accuracy of iterative programming processes. The problem addressed is the variability in convergence rates across different types of memory cells, which can lead to inefficient programming cycles and reduced performance. The solution involves dynamically adjusting the iterative programming process based on the specific type of memory cell being programmed. The system first identifies a subset of memory cells to be programmed and then determines the rate of convergence for the iterative generation process based on the type of memory cell in that subset. This adjustment ensures that the programming process adapts to the characteristics of the memory cells, optimizing convergence speed and accuracy. The method includes iterative programming steps where the programming parameters are refined in each cycle until the desired programming state is achieved. The invention improves memory programming efficiency by tailoring the iterative process to the specific memory cell type, reducing unnecessary cycles and enhancing overall system performance.
20. The non-transitory computer-readable storage medium of claim 15 , wherein the current processing level, the first offset processing level, the second offset processing level, and the updated processing level are all read level voltages.
A system and method for managing read level voltages in non-volatile memory storage devices addresses the challenge of maintaining data integrity and performance as memory cells degrade over time. The invention involves dynamically adjusting read level voltages to compensate for shifts in threshold voltage distributions caused by wear, temperature variations, or other environmental factors. The system monitors the current processing level, which is a read level voltage applied to retrieve data from memory cells. To account for potential errors, the system also evaluates first and second offset processing levels, which are read level voltages slightly higher and lower than the current level. Based on error detection results, the system calculates an updated processing level to optimize read accuracy. All processing levels, including the current, offset, and updated levels, are read level voltages specifically tuned to the characteristics of the memory cells. This adaptive approach ensures reliable data retrieval even as memory cells age, improving the longevity and reliability of non-volatile storage devices. The invention is particularly useful in flash memory, solid-state drives, and other storage technologies where read level adjustments are critical for maintaining performance.
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September 1, 2020
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