Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A memory module comprising: an address buffer circuit; a command/address channel; and a plurality of memory ranks, wherein each rank of the plurality of memory ranks includes a respective plurality of memory components, where at least one of the plurality of memory ranks is controlled by the address buffer circuit via the command/address channel, each memory component of the respective plurality of memory components comprising: a plurality of memory component data ports; a memory core to store data; and for each one of the respective plurality of memory components: a respective data interface to transfer data between the respective memory core and the respective plurality of memory component data ports, the respective data interface supporting a first data width mode in which the respective data interface transfers data at a first bit width and a first burst length via a first set of the respective plurality of memory component data ports, the respective data interface supporting a second data width mode in which the respective data interface transfers data at a second bit width and second burst length via a second set of the respective plurality of memory component data ports that has less memory component data ports than the first set of the respective plurality of memory component data ports, the first bit width greater than the second bit width and the first burst length shorter than the second burst length; a plurality of memory module data pins to transfer the data between the plurality of memory component data ports for all of the respective plurality of memory components of a selected memory rank and a memory controller.
This invention relates to memory modules and addresses the need for efficient data transfer with varying data widths. The memory module includes an address buffer circuit and a command/address channel for controlling memory ranks. It comprises multiple memory ranks, each with multiple memory components. At least one memory rank is managed by the address buffer circuit through the command/address channel. Each memory component contains a memory core for data storage and multiple data ports. A data interface within each component facilitates data transfer between the memory core and its data ports. This interface supports two distinct data transfer modes. The first mode utilizes a larger bit width and a shorter burst length, transferring data through a first set of data ports. The second mode uses a smaller bit width and a longer burst length, employing a second set of data ports that is smaller than the first set. The memory module also has data pins to connect the data ports of all memory components within a selected memory rank to a memory controller, enabling data exchange.
2. The memory module of claim 1 , wherein the second bit width is four bits and the second burst length is sixteen, and the first bit width is eight bits and the first burst length is eight.
This invention relates to memory modules designed to optimize data transfer efficiency in computing systems. The problem addressed is the mismatch between memory module capabilities and processor requirements, leading to inefficiencies in data handling. The solution involves a memory module with configurable bit widths and burst lengths to align with different processing demands. The memory module includes a first interface and a second interface, each supporting different data transfer configurations. The first interface operates with an eight-bit width and an eight-cycle burst length, suitable for applications requiring moderate data throughput. The second interface operates with a four-bit width and a sixteen-cycle burst length, enabling higher sustained data rates for bandwidth-intensive tasks. This dual-interface design allows the module to dynamically adapt to varying workloads, improving overall system performance. The module further includes a controller that manages data routing between the interfaces, ensuring seamless transitions between configurations. This controller may also handle error correction and data validation to maintain integrity during transfers. The invention is particularly useful in high-performance computing, where balancing latency and throughput is critical. By providing flexible data transfer options, the memory module enhances compatibility with diverse processing architectures while minimizing bottlenecks.
3. The memory module of claim 1 , wherein the first set of the respective plurality of memory component data ports include first memory component data ports and second memory component data ports, and in the first data width mode the respective data interface transfers data via the first memory component data ports and the second memory component data ports, and in the second data width mode the respective data interface transfers data via the second set of the respective plurality of memory component data ports that includes the first memory component data ports but not the second memory component data ports.
A memory module includes a plurality of memory components, each with multiple data ports, and a data interface that connects to these ports. The module supports two data width modes: a first mode where data is transferred using all available data ports (both first and second sets) and a second mode where data is transferred using only a subset of the ports (the first set, excluding the second set). This design allows the memory module to dynamically adjust its data transfer width, optimizing performance and power efficiency based on system requirements. The first set of data ports includes both first and second memory component data ports, while the second set includes only the first memory component data ports. In the first mode, data is transferred through all ports, providing higher bandwidth, while in the second mode, data is transferred through only the first set, reducing power consumption or simplifying routing. This flexible configuration enables the memory module to adapt to different operational demands, such as high-speed data processing or low-power operation. The invention addresses the need for memory systems that can balance performance and efficiency in varying workloads.
4. The memory module of claim 1 , wherein: in a memory read operation of the first data width mode, the respective data interface is to transmit a first timing reference signal associated with a first portion of the first bit width, and is to transmit a second timing reference signal associated with a second portion of the first bit width; and in a memory read operation of the second data width mode, the respective data interface is to transmit a timing reference signal associated with all bits of the second bit width.
This invention relates to memory modules with configurable data width modes for optimizing data transmission efficiency. The problem addressed is the need for flexible data transfer in memory systems to accommodate varying bandwidth requirements while maintaining timing accuracy. The memory module includes multiple data interfaces, each supporting at least two data width modes: a first mode with a wider bit width and a second mode with a narrower bit width. In the first mode, during a memory read operation, each data interface transmits two timing reference signals. The first timing reference signal is associated with a first portion of the wider bit width, and the second timing reference signal is associated with a second portion of the wider bit width. This allows for precise timing alignment of the wider data bus. In the second mode, during a memory read operation, each data interface transmits a single timing reference signal associated with all bits of the narrower bit width, simplifying the timing synchronization process for the narrower bus. The invention enables efficient data transfer by dynamically adjusting the number of timing reference signals based on the selected data width mode, improving performance and reducing complexity in memory systems.
5. The memory module of claim 1 , wherein the memory component comprises a mode register to store a setting indicative of a data transfer width, and the data interface operates in the first data width mode or the second data width mode depending on the setting stored in the mode register.
A memory module includes a memory component with a mode register that stores a setting indicating a data transfer width. The module also includes a data interface that operates in either a first data width mode or a second data width mode based on the setting stored in the mode register. The first data width mode may correspond to a narrower data transfer width, such as x4, while the second data width mode may correspond to a wider data width, such as x8 or x16. The mode register allows dynamic configuration of the data transfer width, enabling the memory module to adapt to different system requirements or performance needs. This flexibility can improve compatibility with various host systems or optimize performance based on workload demands. The memory component may include volatile or non-volatile memory, such as DRAM, and the data interface may support standard protocols like DDR, LPDDR, or GDDR. The module may also include additional circuitry, such as a controller or buffer, to manage data transfers and interface with the host system. The ability to switch between different data width modes enhances versatility and efficiency in memory operations.
6. The memory module of claim 1 , further comprising for each one of the respective plurality of memory components: a respective data path between the respective data interface and the respective memory core, the respective data path having a third bit width greater than the first bit width and the second bit width; wherein in both the first data width mode and the second data width mode, the respective data interface writes data to the respective memory core via the respective data path at the third bit width.
This invention relates to memory modules designed to support multiple data width modes while maintaining high-speed data transfer. The problem addressed is the inefficiency of conventional memory modules that operate at fixed data widths, limiting performance in systems requiring flexible data handling. The memory module includes multiple memory components, each with a data interface and a memory core. The data interface operates in either a first or second data width mode, where the first mode uses a first bit width and the second mode uses a second bit width. Each memory component has a dedicated data path between its data interface and memory core, with a third bit width that is larger than both the first and second bit widths. Regardless of the selected data width mode, the data interface writes data to the memory core via this wider data path, ensuring efficient data transfer. This design allows the memory module to adapt to different data width requirements while maintaining high-speed performance by leveraging the wider internal data path. The invention improves flexibility and efficiency in memory operations, particularly in systems that require dynamic adjustments to data width.
7. The memory module of claim 6 , wherein the respective data interface includes: a respective first data receiver circuit corresponding to a portion of the first bit width; a respective second data receiver circuit corresponding to another portion of the first bit width; a respective first deserializer having an input coupled to an output of the respective first data receiver circuit; a respective second deserializer having an input coupled to an output of the respective second data receiver circuit; and a respective multiplexer having a first input coupled to an output of the respective first deserializer and a second input coupled to an output of the respective second deserializer, the respective multiplexer having an output coupled to the data path.
This invention relates to memory modules with high-speed data interfaces designed to handle wide data bit widths efficiently. The problem addressed is the challenge of managing high-speed data transmission and reception in memory systems where the data bit width exceeds the capacity of a single receiver circuit. The solution involves partitioning the data interface into multiple receiver circuits, each handling a portion of the total bit width, followed by deserialization and multiplexing to consolidate the data into a unified data path. The memory module includes a data interface with at least two data receiver circuits, each assigned to a distinct portion of the total bit width. Each receiver circuit is connected to a deserializer, which converts high-speed serial data into parallel data. The outputs of the deserializers are then fed into a multiplexer, which combines the parallel data streams into a single output coupled to the memory module's data path. This architecture allows for scalable and efficient data handling, ensuring that high-speed data transmission is managed without bottlenecks. The design is particularly useful in high-performance computing and memory systems where wide data bit widths are required for optimal performance.
8. The memory module of claim 1 , further comprising for each one of the respective plurality of memory components: a respective data path between the respective data interface and the respective memory core, the respective data path having a third bit width greater than the first bit width and the second bit width; wherein in both the first mode and the second mode, the respective data interface reads data from the respective memory core via the respective data path at the third bit width.
This invention relates to memory modules designed to optimize data transfer efficiency in computing systems. The problem addressed is the mismatch between the bit widths of memory cores and external interfaces, which can lead to inefficiencies in data transfer rates. Traditional memory modules often use narrow data paths between memory cores and interfaces, limiting performance. The memory module includes multiple memory components, each with a memory core and a data interface. The memory core has a first bit width, and the data interface has a second bit width. To improve data transfer, each memory component includes a dedicated data path between its data interface and memory core. This data path has a third bit width, which is wider than both the first and second bit widths. This wider path allows the data interface to read data from the memory core at the third bit width in both a first mode (e.g., normal operation) and a second mode (e.g., a high-performance or diagnostic mode). By using a wider internal data path, the module can enhance data throughput without requiring changes to the external interface or memory core designs. This approach ensures efficient data movement within the module, reducing bottlenecks and improving overall system performance.
9. The memory module of claim 8 , wherein the respective data interface includes: a respective serializer having an input coupled to the respective data path; a respective first multiplexer having an input coupled to an output of the respective serializer; a respective second multiplexer having an input coupled to the output of the respective serializer; a respective first data transmitter circuit having an input coupled to an output of the respective first multiplexer; and a respective second data transmitter circuit having an input coupled to an output of the respective second multiplexer.
This invention relates to memory modules with enhanced data transmission capabilities. The problem addressed is the need for flexible and efficient data routing in high-performance memory systems, particularly where multiple data paths must be managed dynamically. The memory module includes multiple data interfaces, each connected to a respective data path. Each data interface contains a serializer that converts parallel data from the data path into a serial format. The serialized data is then fed into two multiplexers, allowing for selective routing to different transmitter circuits. The first multiplexer directs the data to a first transmitter circuit, while the second multiplexer routes the data to a second transmitter circuit. This dual-multiplexer design enables dynamic switching between transmission paths, improving data throughput and reliability. The transmitter circuits further process the data for output, ensuring compatibility with external systems. The configuration allows for independent control of data flow, enabling features such as redundancy, load balancing, or adaptive routing based on system demands. This architecture is particularly useful in high-speed memory applications where data integrity and transmission efficiency are critical. The modular design ensures scalability, allowing integration into various memory systems without significant redesign.
10. The memory module of claim 1 , wherein the address buffer circuit comprises first command and address input ports and second command and address input ports, and the address buffer selectively routes command and address signals from a selected one of the first command and address input ports and the second command and address input ports to the command and address bus.
A memory module includes an address buffer circuit designed to improve flexibility in command and address signal routing. The circuit features two sets of input ports: first command and address input ports and second command and address input ports. The address buffer selectively routes command and address signals from either the first or second set of input ports to a command and address bus. This selective routing allows the memory module to dynamically switch between different sources of command and address signals, enhancing compatibility with multiple controllers or interfaces. The design supports scenarios where a memory module may need to interface with redundant or alternative control paths, such as in fault-tolerant systems or during testing and debugging. By providing dual input ports, the memory module can maintain functionality even if one input path fails or becomes unavailable, improving reliability. The address buffer circuit ensures that only the selected input port's signals are transmitted to the command and address bus, preventing signal conflicts and ensuring proper operation. This feature is particularly useful in systems requiring high availability or those with complex memory architectures.
11. A memory component comprising: an integrated circuit package comprising: a respective plurality of memory component data ports; a respective memory core to store data; and a respective data interface to transfer data between the respective memory core and the respective plurality of memory component data ports, the respective data interface supporting a first data width mode in which the respective data interface transfers data at a first bit width and a first burst length via a first set of the respective plurality of memory component data ports, the respective data interface supporting a second data width mode in which the respective data interface transfers data at a second bit width and second burst length via a second set of the respective plurality of memory component data ports that has less memory component data ports than the first set of the respective plurality of memory component data ports, the first bit width greater than the second bit width and the first burst length shorter than the second burst length; wherein the respective plurality of memory component data ports are connected to a plurality of memory module data pins of a memory module, the memory module including a memory rank comprising a plurality of memory components that include the memory component, the plurality of memory module data pins to transfer the data between a plurality of memory component data ports for all of the plurality of memory components of the memory rank and a memory controller.
This invention relates to a memory component designed to optimize data transfer efficiency in memory systems. The memory component includes an integrated circuit package with multiple data ports, a memory core for storing data, and a data interface that manages data transfer between the memory core and the data ports. The data interface supports two distinct operating modes: a first mode with a wider bit width and shorter burst length, and a second mode with a narrower bit width and longer burst length. In the first mode, data is transferred using a larger subset of the available data ports, while in the second mode, a smaller subset of data ports is used. The first mode prioritizes higher bandwidth by utilizing more ports for shorter, wider data transfers, while the second mode reduces port usage for longer, narrower transfers, potentially improving efficiency in certain memory access patterns. The memory component is part of a memory rank within a memory module, where its data ports are connected to the module's data pins, facilitating communication with a memory controller. This design allows the memory system to dynamically adjust data transfer characteristics based on workload demands, balancing bandwidth and efficiency.
12. The memory component of claim 11 , wherein the second bit width is four bits and the second burst length is sixteen, and the first bit width is eight bits and the first burst length is eight.
This invention relates to memory components, specifically addressing the configuration of data transfer parameters to optimize performance in memory systems. The problem being solved involves efficiently managing data transactions between memory and processing units, particularly in systems where different memory interfaces or modes require distinct burst lengths and bit widths to balance throughput, latency, and power consumption. The memory component includes a first interface and a second interface, each supporting different data transfer configurations. The first interface operates with an eight-bit width and an eight-cycle burst length, allowing for moderate data throughput with lower latency. The second interface uses a four-bit width and a sixteen-cycle burst length, which may be advantageous for power efficiency or compatibility with certain memory architectures. The component dynamically selects between these configurations based on system requirements, such as the type of data being transferred or the operational state of the memory system. This adaptability ensures optimal performance across varying workloads and memory access patterns. The invention may be applied in embedded systems, high-performance computing, or memory controllers where flexible data transfer modes are needed.
13. The memory component of claim 11 , wherein the first set of the respective plurality of memory component data ports include first memory component data ports and second memory component data ports, and in the first data width mode the respective data interface transfers data via the first memory component data ports and the second memory component data ports, and in the second data width mode the respective data interface transfers data via the second set of the respective plurality of memory component data ports that includes the first memory component data ports but not the second memory component data ports.
A memory component includes a plurality of data ports that can operate in different data width modes to transfer data. The memory component has a first set of data ports, which includes both first and second data ports, and a second set of data ports, which includes only the first data ports. In a first data width mode, data is transferred using both the first and second data ports. In a second data width mode, data is transferred using only the first data ports, effectively reducing the data width. This configuration allows the memory component to dynamically adjust its data transfer capabilities based on operational requirements, such as power efficiency or performance needs. The memory component may be part of a larger system where multiple such components are interconnected, and the data interface between them supports the switching between different data width modes. This design enables flexible data handling, optimizing resource usage and performance in varying conditions.
14. The memory component of claim 11 , wherein: in a memory read operation of the first data width mode, the respective data interface is to transmit a first timing reference signal associated with a first portion of the first bit width, and is to transmit a second timing reference signal associated with a second portion of the first bit width; and in a memory read operation of the second data width mode, the respective data interface is to transmit a timing reference signal associated with all bits of the second bit width.
This invention relates to memory components with configurable data width modes for efficient data transmission. The problem addressed is optimizing memory read operations by dynamically adjusting timing reference signals based on the selected data width mode, improving synchronization and reducing latency. The memory component includes a data interface that supports at least two data width modes: a first mode with a wider bit width and a second mode with a narrower bit width. In the first mode, the data interface transmits two separate timing reference signals—one for a first portion of the wider bit width and another for a second portion. This segmented approach ensures precise synchronization for high-bit-width data transfers. In the second mode, a single timing reference signal is transmitted for the entire narrower bit width, simplifying synchronization for lower-bit-width operations. The invention enhances memory performance by adapting timing references to the data width, reducing overhead in low-width modes while maintaining accuracy in high-width modes. This is particularly useful in systems requiring flexible memory access, such as processors or controllers handling variable data sizes. The solution avoids unnecessary complexity in low-width operations while ensuring reliable synchronization in high-width transfers.
15. The memory component of claim 11 , wherein the integrated circuit package comprises a mode register to store a setting indicative of a data transfer width, and the respective data interface operates in the first data width mode or the second data width mode depending on the setting stored in the mode register.
This invention relates to memory components, specifically integrated circuit packages with configurable data transfer widths. The problem addressed is the need for flexible data interface configurations in memory systems to optimize performance and compatibility with different system architectures. The memory component includes an integrated circuit package with multiple data interfaces, each capable of operating in at least two distinct data width modes. A mode register within the package stores a setting that determines the active data transfer width for each interface. Depending on the stored setting, the interfaces switch between a first data width mode and a second data width mode. This allows the memory component to dynamically adjust its data transfer capabilities based on system requirements, improving efficiency and adaptability. The mode register enables configuration of the data transfer width, ensuring compatibility with various system designs. The interfaces can be individually controlled, allowing for mixed-mode operation where different interfaces operate in different width modes simultaneously. This flexibility supports diverse memory system architectures, including those requiring variable bandwidth or specialized data handling. The invention enhances memory system performance by optimizing data transfer rates and reducing latency through configurable interface modes.
16. The memory component of claim 11 , wherein the integrated circuit package further comprises: a respective data path between the respective data interface and the respective memory core, the respective data path having a third bit width greater than the first bit width and the second bit width; wherein in both the first data width mode and the second data width mode, the respective data interface writes data to the respective memory core via the data path at the third bit width.
This invention relates to memory components in integrated circuit packages, addressing the challenge of efficiently managing data transfer between memory cores and external interfaces. The system includes multiple memory cores, each with a dedicated data interface and a data path connecting the interface to the core. The data path operates at a fixed bit width (third bit width) that is wider than the bit widths of the external interfaces (first and second bit widths). This design allows the memory component to support multiple data width modes (first and second data width modes) while maintaining high-speed data transfer internally. The data interface receives data at the narrower external bit width and writes it to the memory core at the wider internal bit width, ensuring efficient data handling regardless of the external interface's configuration. This approach optimizes performance by reducing bottlenecks in data transfer, particularly in systems requiring flexible data width support. The invention is useful in applications where memory components must adapt to different interface standards while maintaining high throughput.
17. The memory component of claim 16 , wherein the respective data interface comprises: a respective first data receiver circuit corresponding to a portion of the first bit width; a respective second data receiver circuit corresponding to another portion of the first bit width; a respective first deserializer having an input coupled to an output of the respective first data receiver circuit; a second deserializer having an input coupled to an output of the respective second data receiver circuit; a respective multiplexer having a first input coupled to an output of the respective first deserializer and a second input coupled to an output of the respective second deserializer, the respective multiplexer having an output coupled to the data path.
This invention relates to memory components with enhanced data interface capabilities for handling high-speed data transfers. The problem addressed is the efficient processing of wide-bit-width data streams in memory systems, particularly where data must be deserialized and multiplexed to match the memory's internal data path width. The memory component includes a data interface designed to receive and process data from a high-speed data bus. The interface splits the incoming data stream, which has a first bit width, into two portions. Each portion is processed by a dedicated data receiver circuit. The first portion is fed into a first deserializer, while the second portion is fed into a second deserializer. The outputs of these deserializers are then combined using a multiplexer, which selects between the two deserialized data streams and outputs the result to the memory's internal data path. This architecture allows for flexible and efficient data handling, accommodating different data widths and transfer rates while ensuring compatibility with the memory's internal processing requirements. The design optimizes data throughput and reduces latency by parallelizing the deserialization process and dynamically selecting the appropriate data stream.
18. The memory component of claim 11 , wherein the integrated circuit package comprises: a respective data path between the respective data interface and the respective memory core, the respective data path having a third bit width greater than the first bit width and the second bit width; wherein in both the first mode and the second mode, the respective data interface reads data from the respective memory core via the respective data path at the third bit width.
This invention relates to integrated circuit packages with memory components designed to optimize data transfer efficiency. The problem addressed is the inefficiency in data transfer between memory cores and external interfaces, particularly when different bit widths are involved. The solution involves an integrated circuit package with a memory component that includes a data interface and a memory core. The data interface has a first bit width for external communication, while the memory core operates at a second bit width. A dedicated data path connects the data interface to the memory core, with a third bit width that is larger than both the first and second bit widths. This wider data path allows the memory core to read data at the third bit width in both a first mode (e.g., normal operation) and a second mode (e.g., a high-performance or low-power mode). The wider internal data path reduces bottlenecks, improving data transfer rates and overall system efficiency. The memory component may also include control logic to manage data flow between the interface and the core, ensuring compatibility with different bit widths while maintaining high-speed operation. This design is particularly useful in systems requiring fast, efficient memory access, such as high-performance computing or embedded systems.
19. The memory component of claim 18 , wherein the respective data interface comprises: a respective serializer having an input coupled to the respective data path; a respective first multiplexer having an input coupled to an output of the respective serializer; a respective second multiplexer having an input coupled to the output of the respective serializer; a respective first data transmitter circuit having an input coupled to an output of the respective first multiplexer; and a respective second data transmitter circuit having an input coupled to an output of the respective second multiplexer.
This invention relates to memory components with enhanced data transmission capabilities, particularly for systems requiring high-speed data transfer and redundancy. The problem addressed is the need for efficient and reliable data transmission from memory components to external devices, ensuring both performance and fault tolerance. The memory component includes multiple data interfaces, each connected to a respective data path. Each data interface comprises a serializer that converts parallel data from the data path into a serial format for transmission. The serialized data is then fed into two multiplexers, allowing for flexible routing. The first multiplexer directs the data to a first transmitter circuit, while the second multiplexer directs the data to a second transmitter circuit. This dual-transmitter design enables redundancy, ensuring data integrity even if one transmitter fails. The multiplexers can also select between different data sources or modes, providing additional flexibility in data handling. The overall system improves data transmission reliability and performance in memory-intensive applications.
20. The memory component of claim 11 , wherein the first bit width times the first burst length is equal to the second bit width times the second burst length.
This invention relates to memory systems, specifically addressing the challenge of efficiently managing data transfer between memory components with different bit widths and burst lengths. The system includes a memory component configured to receive data from a host device, where the memory component has a first bit width and a first burst length. The host device operates with a second bit width and a second burst length, which may differ from those of the memory component. The memory component includes a buffer to temporarily store data during transfer, ensuring compatibility between the host and memory. The buffer is sized to accommodate the larger of the two burst lengths to prevent data loss. The system also includes a controller that aligns the data transfer by adjusting the burst length or bit width as needed. The invention ensures efficient data transfer by maintaining a relationship where the product of the first bit width and first burst length equals the product of the second bit width and second burst length, ensuring seamless data alignment without overflow or underflow. This solution optimizes memory performance by dynamically adapting to mismatched host and memory configurations, reducing latency and improving reliability.
Unknown
September 1, 2020
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.