Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. For a circuit of a device, the circuit comprising a plurality of neurons, a method for configuring (i) neurons on the circuit and (ii) routing fabric between the neurons on the circuit, in order to implement an interconnected arrangement of neurons that defines a neural network that executes on the device, the method comprising: identifying a defective neuron of the circuit; removing the defective neuron from a group of neurons available for the interconnected arrangement of neurons; in the group, replacing the removed, defective neuron with a redundant neuron of the circuit; and configuring routing fabric to interconnect the neurons in the group to define the interconnected arrangement of neurons, wherein said identifying, removing, replacing and configuring are performed when the device is powered on in order to start operation of the neural network on the device, wherein identifying the defective neuron comprises retrieving from a non-volatile storage of the device an identity of the defective neuron that was stored in the storage during an earlier testing phase of the neural network.
This invention relates to neural network hardware, specifically methods for configuring neuron circuits and routing fabric in a device to implement a neural network while handling defective neurons. The problem addressed is ensuring reliable operation of neural networks on hardware by managing defective components during device startup. The method involves identifying defective neurons by retrieving their identities from non-volatile storage, which were recorded during prior testing. These defective neurons are excluded from the available neuron pool and replaced with redundant neurons. The routing fabric is then configured to interconnect the remaining neurons, forming the desired neural network structure. This process occurs during device power-on to enable immediate and reliable neural network operation. The approach ensures that hardware defects do not disrupt neural network functionality by leveraging pre-recorded defect information and redundant components. The solution is particularly useful in neuromorphic computing systems where hardware defects could otherwise impair neural network performance.
2. The method of claim 1 , wherein the configured routing fabric re-routes signals around the removed, defective neuron.
A neural network system includes a configurable routing fabric that dynamically reconfigures signal paths to bypass defective neurons. The system comprises multiple neurons interconnected by a routing fabric that can be reconfigured to maintain network functionality despite hardware defects. The routing fabric is initially configured to establish signal paths between neurons based on a predefined network architecture. When a neuron is identified as defective, the routing fabric automatically re-routes signals around the defective neuron to alternative paths, ensuring continuous operation of the neural network. The re-routing process involves identifying available alternative paths, determining the optimal path based on signal integrity and latency, and reconfiguring the routing fabric to establish the new signal paths. This approach allows the neural network to maintain performance and reliability even in the presence of hardware failures, extending the system's operational lifespan. The system may include additional features such as error detection mechanisms to identify defective neurons and adaptive routing algorithms to optimize signal paths in real-time. The routing fabric may be implemented using programmable interconnects or switches that can be dynamically reconfigured to reroute signals as needed. This method ensures that the neural network remains functional by dynamically adapting to hardware defects without requiring manual intervention.
3. The method of claim 1 , wherein the configured routing fabric does not provide any signal to or forward any signal from the removed, defective neuron.
This invention relates to neural network systems and addresses the challenge of handling defective neurons in a configurable routing fabric. The routing fabric dynamically connects neurons in a neural network, allowing for flexible communication paths. When a neuron becomes defective, the routing fabric must isolate it to prevent errors while maintaining network functionality. The method involves detecting a defective neuron and then configuring the routing fabric to exclude the defective neuron from signal transmission. Specifically, the routing fabric is adjusted to prevent any signals from being sent to or received from the defective neuron. This ensures that the defective neuron does not disrupt the overall neural network operation. The routing fabric remains functional for all other neurons, allowing the network to continue processing data without interruption. The method may also include steps for identifying the defective neuron, such as error detection mechanisms or performance monitoring. Once identified, the routing fabric is reconfigured to bypass the defective neuron entirely. This approach improves system reliability by isolating faults while preserving the integrity of the neural network's computational pathways. The solution is particularly useful in large-scale neural networks where hardware defects are more likely to occur.
4. The method of claim 1 , wherein the routing fabric includes an output memory for storing outputs of earlier stage neurons that would have been fed to the defective neuron had the neuron not been defective, and configuring the routing fabric comprises routing the stored outputs of the earlier stage neurons to the redundant neuron instead of the defective neuron.
This invention relates to fault-tolerant neural network architectures, specifically addressing the problem of defective neurons in multi-stage neural networks. The system includes a routing fabric designed to bypass defective neurons by rerouting signals through redundant neurons. The routing fabric contains an output memory that stores the outputs of earlier-stage neurons that would have been sent to a defective neuron if it were functional. When a defect is detected, the routing fabric is reconfigured to redirect these stored outputs to a redundant neuron instead of the defective one. This ensures continuous operation of the neural network despite hardware failures. The redundant neuron processes the rerouted inputs, maintaining the network's functionality without requiring retraining or external intervention. The system dynamically adapts to defects by leveraging pre-stored outputs and reconfigurable routing, minimizing performance degradation. This approach is particularly useful in hardware-implemented neural networks where physical defects can occur, such as in FPGA or ASIC-based accelerators. The invention improves reliability and fault tolerance in neural network hardware by enabling seamless substitution of defective neurons with redundant ones.
5. The method of claim 4 , wherein configuring the routing fabric further comprises supplying machine-trained configuration parameters that were defined to configure the defective neuron to the redundant neuron instead of the defective neuron.
The invention relates to neural network systems and addresses the problem of handling defective neurons in a neural network by reconfiguring the network's routing fabric to utilize redundant neurons. In neural networks, individual neurons can become defective due to hardware faults, manufacturing defects, or wear over time. This can degrade performance or cause failures. The invention provides a method to automatically reconfigure the network by replacing defective neurons with redundant ones using machine-trained configuration parameters. The routing fabric of the neural network is dynamically adjusted to reroute signals and data paths originally intended for the defective neuron to a redundant neuron. The configuration parameters are pre-trained using machine learning techniques to ensure optimal performance and compatibility when substituting redundant neurons. This approach improves fault tolerance and extends the operational lifespan of neural network hardware by efficiently utilizing redundant components without manual intervention. The method ensures seamless integration of the redundant neuron into the network's operations, maintaining the intended functionality while bypassing the defective neuron. This solution is particularly useful in large-scale neural network deployments where hardware reliability is critical.
6. For an integrated circuit (IC) comprising a plurality of neurons, a method for configuring (i) neurons on the IC and (ii) routing fabric between the neurons on the IC, in order to implement an interconnected arrangement of neurons that defines a neural network, the method comprising: identifying a defective neuron of the IC; removing the defective neuron from a group of neurons available for the interconnected arrangement of neurons; in the group, replacing the removed, defective neuron with a redundant neuron of the IC; and configuring routing fabric to interconnect the neurons in the group to define the interconnected arrangement of neurons, wherein said identifying, removing, replacing and configuring (i) are performed after a testing phase of the IC to identify defective components of the IC, said testing phase identifying the defective neuron as a defective component of the IC, (ii) are performed before the IC is mounted on a printed circuit board of a device that will use the IC, and (iii) are part of a process for defining a program for configuring the neural network, said program for storing in a storage of the device.
This invention relates to fault-tolerant configuration of neural network integrated circuits (ICs) with redundant neurons. The problem addressed is the presence of defective neurons in ICs, which can disrupt neural network functionality if not properly managed. The solution involves a method to reconfigure the IC after manufacturing testing but before final deployment to bypass defective neurons using redundant ones. The method identifies defective neurons post-testing, removes them from the active neuron group, and replaces them with redundant neurons. The routing fabric between neurons is then reconfigured to maintain the intended neural network architecture. This process occurs during the IC's programming phase, before it is mounted on a device's printed circuit board, ensuring the final neural network operates correctly despite manufacturing defects. The configuration is stored in the device's memory for runtime execution. The approach improves yield and reliability by leveraging on-chip redundancy without requiring physical repairs or external interventions.
7. For a circuit comprising a plurality of neurons, a method for configuring (i) neurons on the circuit and (ii) routing fabric between the neurons on the circuit, in order to implement an interconnected arrangement of neurons that defines a neural network, the method comprising: identifying a defective neuron of the circuit; removing the defective neuron from a group of neurons available for the interconnected arrangement of neurons; in the group, replacing the removed, defective neuron with a redundant neuron of the circuit; and configuring routing fabric to interconnect the neurons in the group to define the interconnected arrangement of neurons, wherein the plurality of neurons is a smaller, first plurality of physical neurons of the circuit, wherein the interconnected arrangement of neurons is a logical interconnected arrangement of neurons that comprises a larger, second plurality of logical neurons that are implemented on the circuit by iteratively reconfiguring different sets of the physical neurons in the first plurality of physical neurons, and wherein the circuit comprises at least one redundant neuron for each set of physical neurons that is configured more than once to implement two different sets of logical neurons in the logical interconnected arrangement.
This invention relates to fault-tolerant neural network hardware, specifically methods for configuring neuron circuits and routing fabric to maintain functionality despite defective components. The problem addressed is the presence of defective neurons in hardware-implemented neural networks, which can disrupt network operation if not managed. The solution involves dynamically reconfiguring the network to bypass faulty neurons while utilizing redundant components to maintain the intended logical structure. The method operates on a circuit containing multiple physical neurons, some of which may be defective. When a defective neuron is identified, it is removed from the available pool and replaced with a redundant neuron. The routing fabric is then reconfigured to interconnect the remaining neurons, forming the desired neural network. The system uses a smaller number of physical neurons to implement a larger logical network by reconfiguring the same physical neurons for different logical roles. Redundant neurons are provided to ensure that physical neurons used in multiple logical roles do not fail, allowing the network to maintain its intended structure despite defects. This approach enables reliable operation of neural networks in hardware despite manufacturing defects or runtime failures.
8. The method of claim 7 , wherein the circuit is an integrated circuit (IC) and said identifying, removing, replacing and configuring are performed after a testing phase of the IC to identify defective components of the IC, said testing phase identifying the defective neuron as a defective component of the IC.
This technical summary describes a method for repairing defective components in an integrated circuit (IC) designed for neuromorphic computing or similar applications. The method addresses the problem of defective components, such as neurons, within an IC that can impair its functionality. The process involves identifying defective components after a testing phase, where the IC is evaluated to detect faults. Once a defective neuron is identified, it is removed from the circuit and replaced with a functional component. The replacement component is then configured to ensure proper integration into the existing circuit. This method allows for post-fabrication repair of the IC, improving yield and reliability by correcting defects that may have occurred during manufacturing. The approach is particularly useful in complex ICs where individual components, such as neurons in neuromorphic systems, must function correctly for the overall circuit to operate as intended. By performing these steps after testing, the method ensures that only verified defective components are addressed, minimizing unnecessary modifications and maintaining circuit integrity.
9. A non-transitory machine readable medium storing a program for configuring a plurality of neurons and routing fabric between the neurons to form an interconnected arrangement of neurons that defines a neural network for execution on a device, wherein the plurality of neurons and routing fabric are part of a circuit of the device, the program comprising sets of instructions for: identifying a defective neuron of the circuit; removing the defective neuron from a group of neurons available for the interconnected arrangement of neurons; in the group, replacing the removed, defective neuron with a redundant neuron of the circuit; and configuring a routing fabric to interconnect the neurons in the group to define the interconnected arrangement of neurons, wherein the sets of instructions for identifying, removing, replacing and configuring are executed on the device when the device is powered on in order to start operation of the neural network on the device, wherein the set of instructions for identifying the defective neuron comprises a set of instructions for retrieving from a non-volatile storage of the device an identity of the defective neuron that was stored in the storage during an earlier testing phase of the neural network.
This invention relates to fault-tolerant neural network hardware, specifically a method for configuring a neural network circuit to bypass defective neurons using redundant components. The problem addressed is the presence of defective neurons in hardware-based neural networks, which can disrupt network functionality. The solution involves a program stored on a non-volatile medium that configures the neural network during device startup by identifying defective neurons, removing them from the active network, and replacing them with redundant neurons. The routing fabric between neurons is then reconfigured to maintain the intended network topology. The defective neuron identity is retrieved from non-volatile storage, which was previously recorded during an earlier testing phase. This approach ensures the neural network operates correctly despite hardware defects, improving reliability in embedded or specialized hardware implementations. The configuration process occurs automatically when the device powers on, ensuring seamless operation without manual intervention. The invention is particularly useful in applications where hardware defects are likely, such as in large-scale or high-density neural network circuits.
10. The non-transitory machine readable medium of claim 9 , wherein the configured routing fabric re-routes signals around the removed, defective neuron.
The invention relates to fault-tolerant neural network hardware systems, specifically addressing the problem of maintaining functionality when individual neurons become defective. Neural networks implemented in hardware often suffer from permanent or temporary failures in individual neurons, which can disrupt signal processing and degrade performance. The invention provides a solution by incorporating a reconfigurable routing fabric within the neural network hardware. This routing fabric dynamically detects defective neurons and automatically re-routes signals around them to maintain network functionality. The routing fabric is designed to adapt to the network's topology, ensuring that signals bypass faulty components without requiring external intervention. This approach enhances reliability in hardware-based neural networks, particularly in applications where continuous operation is critical, such as embedded systems or real-time processing environments. The re-routing mechanism is implemented in a non-transitory machine-readable medium, allowing the system to store and execute the necessary instructions for fault detection and signal re-routing. The invention ensures that the neural network remains operational even when individual neurons fail, improving overall system robustness.
11. The non-transitory machine readable medium of claim 9 , wherein the configured routing fabric does not provide any signal to or forward any signal from the removed, defective neuron.
The invention relates to a machine-readable medium storing instructions for a neural network system with a configurable routing fabric. The system addresses the challenge of handling defective neurons in neural networks by dynamically isolating faulty components without disrupting overall network functionality. The routing fabric is configured to detect and remove defective neurons, ensuring that no signals are sent to or received from the faulty neuron. This isolation prevents error propagation while maintaining the integrity of the neural network's operations. The routing fabric dynamically adjusts signal paths to bypass the defective neuron, allowing the network to continue processing tasks without interruption. The system is particularly useful in large-scale neural networks where hardware defects or manufacturing imperfections may occur, ensuring robustness and reliability in real-world applications. The machine-readable medium contains instructions that, when executed, enable the routing fabric to identify defective neurons and reconfigure signal routing accordingly, optimizing performance and fault tolerance.
12. The non-transitory machine readable medium of claim 9 , wherein the routing fabric includes an output memory for storing outputs of earlier stage neurons that would have been fed to the defective neuron had the neuron not been defective, and the set of instructions for configuring the routing fabric comprises a set of instructions for routing the stored outputs of the earlier stage neurons to the redundant neuron instead of the defective neuron.
The invention relates to fault-tolerant neural network architectures, specifically addressing the problem of defective neurons in hardware-implemented neural networks. Neural networks deployed in hardware systems may suffer from defects in individual neurons, which can disrupt the flow of data and degrade performance. The invention provides a solution by incorporating a redundant neuron to replace defective neurons and a routing fabric to dynamically reroute data around the defect. The routing fabric includes an output memory that stores the outputs of earlier-stage neurons that would have been sent to the defective neuron. Instead of transmitting these outputs to the defective neuron, the routing fabric reroutes them to a redundant neuron. This ensures that the neural network continues to function correctly despite the presence of defects. The routing fabric is configurable via a set of instructions that specify how data should be rerouted to bypass the defective neuron and utilize the redundant neuron instead. This approach improves reliability in hardware-based neural networks by dynamically compensating for defects without requiring manual intervention or redesign.
13. The non-transitory machine readable medium of claim 12 , wherein the set of instructions for configuring the routing fabric further comprises a set of instructions for supplying machine-trained configuration parameters for configuring the defective neuron to the redundant neuron instead of the defective neuron.
The invention relates to a machine-readable medium storing instructions for configuring a routing fabric in a neural network system, particularly addressing the problem of handling defective neurons by leveraging redundant neurons. The system includes a neural network with a routing fabric that connects neurons, where some neurons may become defective during operation. The medium stores instructions for detecting defective neurons and reconfiguring the routing fabric to bypass the defective neuron by routing signals through a redundant neuron. The instructions further include supplying machine-trained configuration parameters to the redundant neuron, ensuring it operates in place of the defective neuron without requiring retraining. This approach maintains the neural network's functionality by dynamically reconfiguring the routing fabric and transferring the learned parameters to the redundant neuron, thereby improving reliability and reducing downtime. The solution is particularly useful in large-scale neural networks where hardware defects are common, ensuring continuous operation by seamlessly replacing defective components with pre-configured redundancies.
14. A non-transitory machine readable medium storing a program for configuring a plurality of neurons and routing fabric between the neurons to form an interconnected arrangement of neurons that defines a neural network, wherein the plurality of neurons and routing fabric are part of an integrated circuit (IC), the program comprising sets of instructions for: identifying a defective neuron of the IC; removing the defective neuron from a group of neurons available for the interconnected arrangement of neurons; in the group, replacing the removed, defective neuron with a redundant neuron of the IC; and configuring a routing fabric to interconnect the neurons in the group to define the interconnected arrangement of neurons; wherein the sets of instructions for identifying, removing, replacing and configuring (i) are executed after a testing phase of the IC to identify defective components of the IC, said testing phase identifying the defective neuron as a defective component of the IC, (ii) are executed before the IC is mounted on a printed circuit board of a device that will use the IC, and (iii) are part of a process for defining another program for configuring the neural network, said other program for storing in a storage of the device.
This invention relates to fault-tolerant neural network configurations in integrated circuits (ICs). The problem addressed is the presence of defective neurons in IC-based neural networks, which can degrade performance or render the network unusable. The solution involves a program stored on a non-transitory machine-readable medium that configures neurons and routing fabric within an IC to form a functional neural network despite defects. The program identifies defective neurons during a post-manufacturing testing phase, removes them from the available pool of neurons, and replaces them with redundant neurons also present in the IC. The routing fabric is then reconfigured to interconnect the remaining neurons, including the redundant ones, to form the desired neural network structure. This process occurs after the IC is tested but before it is mounted on a device's printed circuit board. The resulting configuration is stored as another program in the device's storage, defining the operational neural network. The approach ensures that defective neurons do not compromise the network's functionality by leveraging redundancy and dynamic reconfiguration, improving yield and reliability in IC-based neural network implementations.
15. A non-transitory machine readable medium storing a program for configuring a plurality of neurons and routing fabric between the neurons to form an interconnected arrangement of neurons that defines a neural network, wherein the plurality of neurons and routing fabric are part of a circuit, the program comprising sets of instructions for: identifying a defective neuron of the circuit; removing the defective neuron from a group of neurons available for the interconnected arrangement of neurons; in the group, replacing the removed, defective neuron with a redundant neuron of the circuit; and configuring a routing fabric to interconnect the neurons in the group to define the interconnected arrangement of neurons; wherein the plurality of neurons is a smaller, first plurality of physical neurons of the circuit, wherein the interconnected arrangement of neurons is a logical interconnected arrangement of neurons that comprises a larger, second plurality of logical neurons that are implemented on the circuit by iteratively reconfiguring different sets of the physical neurons in the first plurality of physical neurons, and wherein the circuit comprises at least one redundant neuron for each set of physical neurons that is configured more than once to implement two different sets of logical neurons in the logical interconnected arrangement.
This invention relates to fault-tolerant neural network hardware, specifically a method for dynamically reconfiguring a neural network circuit to bypass defective neurons. The problem addressed is the presence of defective neurons in hardware-based neural networks, which can disrupt network functionality. The solution involves a program stored on a non-transitory machine-readable medium that configures neurons and routing fabric to form a neural network while accommodating defects. The system includes a circuit with a plurality of physical neurons and routing fabric. The program identifies defective neurons and removes them from the available pool. Redundant neurons in the circuit replace the defective ones, ensuring the network remains functional. The routing fabric is then reconfigured to interconnect the remaining neurons, forming the desired neural network structure. The physical neurons are fewer than the logical neurons in the network, as the same physical neurons are reused to implement multiple logical neurons through iterative reconfiguration. The circuit includes redundant neurons to ensure that physical neurons used more than once to implement different logical neurons have backup options. This approach allows the network to maintain functionality despite hardware defects, improving reliability in neural network hardware implementations.
16. The non-transitory machine readable medium of claim 15 , wherein the circuit is an integrated circuit (IC) and the sets of instruction for identifying, removing, replacing and configuring are executed after a testing phase of the IC to identify defective components of the IC, said testing phase identifying the defective neuron as a defective component of the IC.
This invention relates to a non-transitory machine-readable medium storing instructions for repairing defective components in an integrated circuit (IC), specifically targeting defective neurons in neuromorphic computing systems. The technology addresses the challenge of post-fabrication defects in ICs, particularly in neuromorphic architectures where individual neurons may fail or malfunction. The medium contains sets of instructions for identifying, removing, replacing, and configuring components within the IC. These instructions are executed after a testing phase that detects defective neurons as part of the IC's quality assurance process. The system dynamically reconfigures the IC by isolating faulty neurons and substituting them with functional alternatives, ensuring the IC maintains its intended functionality despite manufacturing defects. This approach improves yield and reliability in neuromorphic hardware by enabling on-chip repair mechanisms without requiring physical rework. The solution is particularly valuable for large-scale neuromorphic systems where even minor defects can significantly impact performance.
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September 1, 2020
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