Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. An electroluminescent display comprising: pixels connected to gate lines; and a gate driving circuit to supply a gate signal to at least one of the gate lines, and composed of a plurality of stages connected to each other in a cascading way, wherein an nth (n is a positive integer) stage of the gate driving circuit comprises: a Q1 node charging unit to charge a Q1 node to a turn-on voltage using a first and a second clock signal, a pull-up transistor to apply a turn-on voltage to an output terminal in response to a voltage of the Q1 node, a pull-down unit to control the output terminal to output a turn-off voltage in response to a voltage of a QB1 node; and a node controller to control the voltage of the QB1 node to a level opposite to a level of the voltage of the Q1 node, wherein the Q1 node charging unit comprises: a first charging unit to charge the voltage of the Q1 node to a turn-on voltage using the second clock signal, and a second charging unit to charge a Q2 node, coupled to the Q1 node, using the first clock signal in a section where the Q1 node has a turn-on voltage, wherein the node controller comprises: a QB2 node controller to apply a turn-on voltage of the first clock signal to a QB2 node in response to a voltage of a QP node, and wherein the QB2 node controller further comprises: a second capacitor connected between the QP node and the QB2 node; and a QP node controller connected between a QB2 node of a (n- 1 )th stage and the QP node.
2. The electroluminescent display of claim 1 , wherein the first charging unit comprises a first transistor connected between a start signal input terminal and the Q1 node and having a gate electrode connected to an input terminal of the second clock signal, wherein the second charging unit comprises a second transistor connected between an input terminal of the first clock signal and the Q2 node and having a gate electrode connected to the Q1 node, and a first capacitor connected between the Q1 node and the Q2 node.
This invention relates to electroluminescent displays, specifically addressing the need for improved control circuitry in display driver circuits. The technology focuses on a shift register unit circuit designed to generate scan signals for driving pixels in an electroluminescent display, such as an OLED display. The problem being solved involves achieving stable and reliable signal generation while minimizing power consumption and circuit complexity. The invention describes a shift register unit circuit with two charging units. The first charging unit includes a first transistor connected between a start signal input terminal and a first node (Q1). The gate electrode of this transistor is connected to an input terminal of a second clock signal. The second charging unit comprises a second transistor connected between an input terminal of a first clock signal and a second node (Q2), with its gate electrode connected to the first node (Q1). Additionally, a first capacitor is connected between the first node (Q1) and the second node (Q2). This configuration ensures proper charging and discharging of the nodes, enabling accurate signal generation for driving display pixels. The circuit leverages clock signals to control the transistors, ensuring synchronized operation and reducing power loss. The capacitor helps maintain voltage levels at the nodes, improving signal stability. This design enhances the efficiency and reliability of the shift register unit in electroluminescent displays.
3. The electroluminescent display of claim 1 , wherein the node controller further comprises a QB1 node controller connected to an input terminal of the first clock signal, from which a gate electrode is applied with the first clock signal, and to apply a voltage of the QB2 node to the QB1 node.
An electroluminescent display includes a pixel circuit with a node controller that manages voltage levels at specific nodes to control light emission. The node controller comprises a QB1 node controller connected to an input terminal of a first clock signal. The QB1 node controller receives the first clock signal at its gate electrode and applies a voltage from a QB2 node to the QB1 node. This configuration ensures proper timing and voltage distribution within the pixel circuit, enabling stable and efficient light emission. The QB1 node controller synchronizes with the first clock signal to regulate the voltage at the QB1 node, which interacts with the QB2 node to maintain desired electrical conditions. This design improves the reliability and performance of the electroluminescent display by ensuring accurate voltage control and timing synchronization. The node controller's structure and connections optimize the display's operation, particularly in managing the electrical states required for consistent light output.
4. The electroluminescent display of claim 1 , wherein the first and second clock signals are in reverse-phase.
An electroluminescent display system includes a plurality of pixels, each pixel having a light-emitting element and a driving circuit. The driving circuit controls the light emission of the element based on data signals and clock signals. The system generates first and second clock signals that are in reverse-phase, meaning they are out of phase by 180 degrees. These clock signals are used to drive the pixel circuits, ensuring synchronized and efficient light emission. The reverse-phase relationship between the clock signals helps reduce power consumption and improve display performance by minimizing signal interference and ensuring precise timing control. The display system may also include a data driver circuit that provides data signals to the pixels, and a scan driver circuit that distributes the clock signals to the pixel circuits. The reverse-phase clock signals are particularly useful in active-matrix electroluminescent displays, where precise timing is critical for maintaining image quality and reducing power usage. The system may further include a timing controller that generates the clock signals and coordinates their distribution to the pixel circuits. The reverse-phase configuration ensures that the clock signals do not overlap, preventing signal conflicts and enhancing the overall efficiency of the display.
5. The electroluminescent display of claim 1 , wherein one cycle of each of the first and the second clock signals is two horizontal periods.
An electroluminescent display system addresses the challenge of efficiently driving display elements to achieve high-quality visual output. The system includes a display panel with multiple pixels, each containing an electroluminescent element and a driving circuit. The driving circuit controls the light emission of the electroluminescent element based on data signals and clock signals. The system generates first and second clock signals to synchronize the operation of the driving circuits. Each cycle of these clock signals corresponds to two horizontal periods, ensuring precise timing for data processing and light emission. The driving circuit includes a data sampling circuit that captures data signals during a first phase of the clock cycle and a driving circuit that activates the electroluminescent element during a second phase. This dual-phase operation allows for stable and accurate control of light emission, improving display performance. The system also includes a scan driver that sequentially selects rows of pixels for data writing and a data driver that provides the necessary data signals. The clock signals ensure synchronized operation between the scan driver, data driver, and driving circuits, enabling efficient and reliable display operation. This design enhances the overall performance of electroluminescent displays by optimizing timing control and data handling.
6. An electroluminescent display comprising: pixels connected to gate lines; and a gate driving circuit to supply a gate signal to at least one of the gate lines, and composed of a plurality of stages connected to each other in a cascading way, wherein an nth (n is a positive integer) stage of the gate driving circuit comprises: a Q1 node charging unit to charge a Q1 node to a turn-on voltage using a first and a second clock signal, a pull-up transistor to apply a turn-on voltage to an output terminal in response to a voltage of the Q1 node, a pull-down unit to control the output terminal to output a turn-off voltage in response to a voltage of a QB1 node; and a node controller to control the voltage of the QB1 node to a level opposite to a level of the voltage of the Q1 node, wherein the pull-down unit is configured as double buffers, wherein the double buffers comprises two transistors, and the two transistors comprise gate electrodes connected to different nodes and output the turn-off voltage.
This invention relates to an electroluminescent display with an improved gate driving circuit. The display includes pixels connected to gate lines and a gate driving circuit that supplies gate signals to these lines. The gate driving circuit is composed of multiple stages connected in a cascading manner. Each stage (nth stage, where n is a positive integer) includes several key components: a Q1 node charging unit that charges a Q1 node to a turn-on voltage using first and second clock signals, a pull-up transistor that applies a turn-on voltage to an output terminal based on the voltage of the Q1 node, a pull-down unit that controls the output terminal to output a turn-off voltage in response to the voltage of a QB1 node, and a node controller that ensures the voltage of the QB1 node is opposite to that of the Q1 node. The pull-down unit is designed as double buffers, consisting of two transistors with gate electrodes connected to different nodes, both outputting the turn-off voltage. This configuration enhances the stability and reliability of the gate driving circuit by preventing unwanted voltage fluctuations and ensuring proper signal transmission to the pixels. The invention addresses issues in conventional gate driving circuits, such as signal distortion and power inefficiency, by improving the pull-down unit's structure and control mechanism.
7. The electroluminescent display of claim 6 , wherein the pull-down unit comprises: a first pull-down transistor operates in response to an electric potential of the QB1 node; and a second pull-down transistor operates in response to the electric potential of a QB2 node.
An electroluminescent display includes a pixel circuit with a pull-down unit designed to stabilize voltage levels during operation. The pull-down unit contains a first pull-down transistor that activates based on the electric potential of a QB1 node and a second pull-down transistor that activates based on the electric potential of a QB2 node. These transistors help control the discharge of voltage in the pixel circuit, preventing unwanted voltage fluctuations that could degrade display performance. The pull-down unit ensures proper voltage regulation, which is critical for maintaining consistent brightness and color accuracy in electroluminescent displays, such as OLED or microLED displays. The transistors in the pull-down unit operate in response to control signals derived from the QB1 and QB2 nodes, which are part of a larger control circuit that manages the timing and voltage levels within the pixel. This design helps mitigate issues like voltage leakage and flickering, improving the overall reliability and visual quality of the display. The pull-down unit is integrated into the pixel circuit to provide localized voltage control, ensuring stable operation across the entire display panel.
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September 1, 2020
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