Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. An inspection method for a memory integrity, comprising: obtaining a threshold voltage of at least one memory cell to-be-inspected in a non-volatile memory; determining a data value belonging to the at least one memory cell to-be-inspected by comparing a read voltage and the threshold voltage, wherein the data value has a first logic state when the threshold voltage is greater than the read voltage, and the data value has a second logic state when the threshold voltage is not greater than the read voltage; setting preset voltage according to the data value when the data value belonging to the at least one memory cell to-be-inspected is determined; obtaining an offset data value belonging to the at least one memory cell by comparing the preset voltage and the threshold voltage of the at least one memory cell to-be-inspected, wherein the offset data value has the first logic state when the threshold voltage of the at least one memory cell to-be-inspected is greater than the preset voltage, and the offset data value has the second logic state when the threshold voltage of the at least one memory cell to-be-inspected is not greater than the preset voltage; determining whether the data value belonging to the at least one memory cell to-be-inspected and the offset data value belonging to the at least one memory cell to-be-inspected are the same; and determining that the integrity of the memory cell to-be-inspected is not defective in response to determining that the data value belonging to the at least one memory cell to-be-inspected and the offset data value belonging to the at least one memory cell to-be-inspected are the same.
Non-volatile memory integrity inspection. This method addresses the problem of verifying the reliability of memory cells. The process involves acquiring the threshold voltage of a memory cell under inspection. A data value is then determined for this cell by comparing a read voltage to its threshold voltage. Specifically, if the threshold voltage is higher than the read voltage, the data value is assigned a first logic state; otherwise, it is assigned a second logic state. Based on this determined data value, a preset voltage is established. Subsequently, an offset data value for the memory cell is obtained by comparing this preset voltage to the cell's threshold voltage. The offset data value receives the first logic state if the threshold voltage exceeds the preset voltage, and the second logic state otherwise. The method then compares the initially determined data value and the derived offset data value. If these two values are identical, it is concluded that the memory cell's integrity is not compromised.
2. The inspection method according to claim 1 , further comprising: determining that the integrity of the memory cell to-be-inspected is defective in response to determining that the data value belonging to the at least one memory cell to-be-inspected and the offset data value belonging to the at least one memory cell to-be-inspected are different.
This technical summary describes a method for inspecting memory cells to detect defects. The method operates in the domain of memory integrity verification, addressing the problem of identifying defective memory cells that may fail to store or retrieve data correctly. The method involves comparing a data value stored in a memory cell with an offset data value derived from the same cell. If the two values differ, the memory cell is determined to be defective. The offset data value is generated by applying a predefined offset to the original data value, allowing for a comparison that can detect errors in the stored data. This approach ensures that even small deviations from expected values can be identified, improving the reliability of memory systems. The method is particularly useful in applications where data integrity is critical, such as in computing systems, storage devices, and embedded systems. By systematically checking each memory cell against its offset counterpart, the method provides a robust mechanism for detecting and flagging defective cells, thereby enhancing the overall reliability of memory operations.
3. The inspection method according to claim 1 , further comprising: sensing a data integrity diagnosis command to the non-volatile memory; sending a first data read command to the non-volatile memory to obtain status data of a status register in the non-volatile memory and determining whether the non-volatile memory completes the data integrity diagnosis command according to a busy bit in the status data, wherein the busy bit is configured to indicate whether a memory data integrity inspection is being performed on the non-volatile memory; sending a second data read command to the non-volatile memory when the data integrity diagnosis command is completed to obtain an integrity verification bit in the status data of the status register; and determining an integrity of a plurality of memory cells in the non-volatile memory is defective according to the integrity verification bit to determine, wherein the memory cells comprise the at least one memory cell to-be-inspected.
This invention relates to a method for inspecting data integrity in non-volatile memory, addressing the challenge of efficiently verifying the integrity of stored data without disrupting normal memory operations. The method involves issuing a data integrity diagnosis command to the non-volatile memory, which triggers an internal inspection process. A first read command retrieves status data from a status register, including a busy bit that indicates whether the memory is currently performing a data integrity check. If the busy bit shows the inspection is complete, a second read command fetches an integrity verification bit from the status register. This bit determines whether the memory cells, including those targeted for inspection, contain defective data. The method ensures that the integrity check is non-intrusive, allowing the memory to continue normal operations while verifying data reliability. The status register provides real-time feedback on the inspection progress and results, enabling quick identification of potential data corruption. This approach is particularly useful in systems requiring high reliability, such as embedded storage or industrial applications, where unnoticed data errors could lead to system failures.
4. The inspection method according to claim 3 , wherein the first data read command is instructed to read parts of bits in the status data.
The invention relates to a method for inspecting memory devices, particularly focusing on efficiently reading status data from a memory device to determine its operational state. The problem addressed is the need to quickly and accurately assess the status of a memory device without performing a full read operation, which can be time-consuming and resource-intensive. The method involves sending a first data read command to the memory device, where this command is specifically configured to read only parts of the bits in the status data rather than the entire data set. This partial read operation allows for a faster and more targeted inspection of critical status information, such as error flags or operational indicators, without the overhead of reading unnecessary data. The method may also include a second data read command to read the remaining parts of the status data if further inspection is required. By selectively reading only the necessary portions of the status data, the method improves efficiency and reduces latency in memory device diagnostics and monitoring. This approach is particularly useful in systems where quick status checks are essential, such as in high-performance computing or real-time applications.
5. The inspection method according to claim 3 , wherein the second data read command is instructed to read another parts of bits in the status data, wherein the parts of bits in the status data are different form the another parts of bits in the status data.
This technical summary describes a method for inspecting memory devices, particularly focusing on reading status data from a memory device to determine its operational state. The method addresses the challenge of efficiently and accurately retrieving status information from memory devices, which is crucial for diagnosing errors, monitoring performance, and ensuring data integrity. The method involves issuing a first data read command to read a first set of bits in the status data stored in the memory device. The status data contains multiple parts of bits, each representing different aspects of the device's status, such as error flags, operational modes, or health indicators. After reading the first set of bits, a second data read command is issued to read a second, distinct set of bits in the status data. The second set of bits differs from the first set, allowing for a comprehensive inspection of the memory device's status by accessing different portions of the status data in separate read operations. This approach enables a more detailed and flexible inspection process, as it allows for selective reading of specific status data segments rather than retrieving the entire status data at once. This can improve efficiency, reduce unnecessary data transfers, and provide more targeted diagnostics. The method is particularly useful in systems where memory devices store status information in a structured format, and where different parts of the status data are relevant for different diagnostic or monitoring purposes.
6. The inspection method according to claim 3 , wherein the status data has 16 bits, first data read command is instructed to read a zero bit to a seventh bit in the status data, and the second data read command is instructed to an eighth bit to a fifteenth bit in the status data.
This invention relates to a method for inspecting status data in a memory device, particularly focusing on efficiently reading status information stored in a 16-bit register. The problem addressed is the need to access specific portions of status data without reading the entire register, which can improve efficiency and reduce unnecessary data transfers. The method involves issuing two distinct data read commands to access different segments of the 16-bit status data. The first command reads the lower 8 bits (bits 0 to 7), while the second command reads the upper 8 bits (bits 8 to 15). This segmented approach allows for selective access to relevant portions of the status data, which can be useful in applications where only certain bits are needed for monitoring or control purposes. The method ensures that only the required bits are retrieved, optimizing performance and reducing overhead in systems where status data is frequently checked. The invention is particularly useful in embedded systems, memory controllers, or other applications where status registers are used to monitor device conditions, error states, or operational parameters. By splitting the read operation into two targeted commands, the method avoids unnecessary processing of irrelevant data, improving efficiency in real-time systems. The technique can be applied to various types of memory devices, including flash memory, SRAM, or other storage technologies where status information is stored in a register.
7. The inspection method according to claim 3 , wherein the busy bit is presented by logic “1” if the non-volatile memory is performing operations, and the busy bit is presented by logic “0” if the non-volatile memory does not perform any operation.
This technical summary describes a method for monitoring the operational status of a non-volatile memory (NVM) device. The method addresses the need to efficiently determine whether the NVM is actively performing operations, such as read, write, or erase cycles, to avoid conflicts or errors during concurrent access. The method involves using a busy bit to indicate the operational state of the NVM. The busy bit is set to logic "1" when the NVM is actively performing operations, signaling that the memory is busy and should not be accessed. Conversely, the busy bit is set to logic "0" when the NVM is idle, indicating that it is safe to initiate new operations. This binary status allows external systems or controllers to synchronize access requests with the NVM's availability, preventing data corruption or failed operations due to concurrent access. The busy bit is dynamically updated by the NVM's internal control logic to reflect its current state. This ensures real-time monitoring of the memory's operational status, enabling efficient resource management in systems where multiple components may need to interact with the NVM. The method is particularly useful in embedded systems, storage devices, and other applications where reliable and conflict-free memory access is critical.
8. A non-volatile memory, comprising: a memory array, comprising a plurality of memory cells; and a control circuit, coupled to the memory array, wherein the control circuit performs memory data integrity inspection to obtain a threshold voltage of at least one memory cell to-be-inspected among the memory cells, determines a data value belonging to the at least one memory cell to-be-inspected by comparing a read voltage and the threshold voltage, wherein the data value has a first logic state when the threshold voltage is greater than the read voltage, and the data value has a second logic state when the threshold voltage is not greater than the read voltage, sets preset voltage according to the data value when the data value belonging to the at least one memory cell to-be-inspected is determined, obtains an offset data value belonging to the at least one memory cell to-be-inspected by comparing the preset voltage and the threshold voltage of the at least one memory cell to-be-inspected, wherein the offset data value has the first logic state when the threshold voltage of the at least one memory cell to-be-inspected is greater than the preset voltage, and the offset data value has the second logic state when the threshold voltage of the at least one memory cell to-be-inspected is not greater than the preset voltage, determines whether the data value belonging to the at least one memory cell to-be-inspected and the offset data value belonging to the at least one memory cell to-be-inspected are the same, and determines that the integrity of the memory cell to-be-inspected is not defective in response to determining that the data value belonging to the at least one memory cell to-be-inspected and the offset data value belonging to the at least one memory cell to-be-inspected are the same.
Non-volatile memory systems, such as flash memory, are prone to data corruption due to wear, electrical noise, or other environmental factors. To ensure data integrity, these systems require mechanisms to detect and verify the reliability of stored data. A non-volatile memory system includes a memory array with multiple memory cells and a control circuit that performs data integrity inspections. The control circuit reads the threshold voltage of a selected memory cell and compares it to a read voltage to determine the stored data value. If the threshold voltage exceeds the read voltage, the data value is assigned a first logic state (e.g., '1'); otherwise, it is assigned a second logic state (e.g., '0'). The control circuit then sets a preset voltage based on the determined data value and compares this preset voltage to the memory cell's threshold voltage to obtain an offset data value. If the threshold voltage is greater than the preset voltage, the offset data value is the first logic state; otherwise, it is the second logic state. The control circuit then checks whether the original data value and the offset data value match. If they do, the memory cell is deemed non-defective, indicating data integrity. This method enhances reliability by cross-verifying stored data against a dynamically adjusted reference voltage.
9. The non-volatile memory according to claim 8 , further comprising: a status register, storing status data, wherein the status data comprises a busy bit and an integrity verification bit, wherein the busy bit is configured to indicate whether the memory data integrity inspection is being performed on the non-volatile memory, and the integrity verification bit is configured to indicate whether integrities of the memory cells in the memory array are defective.
This invention relates to non-volatile memory systems with enhanced data integrity verification features. The technology addresses the challenge of ensuring reliable data storage and retrieval in non-volatile memory devices, particularly in environments where data corruption or integrity issues may arise. The system includes a memory array with memory cells for storing data and a controller configured to perform memory data integrity inspections. The controller executes a data integrity inspection process that involves reading data from the memory cells, performing an integrity verification operation on the read data, and determining whether the data is corrupted or defective. The system also includes a status register that stores status data, which comprises a busy bit and an integrity verification bit. The busy bit indicates whether a memory data integrity inspection is currently being performed on the non-volatile memory. The integrity verification bit indicates whether the integrities of the memory cells in the memory array are defective. This allows the system to monitor and report the status of data integrity checks, providing users or other components with real-time information about the memory's operational state and data reliability. The invention improves fault detection and system robustness by integrating these status indicators into the memory controller's functionality.
10. The non-volatile memory according to claim 9 , wherein the control circuit transmits the status data including the busy bit to a controller through the status register when the first data read command send from the controller is received by the control circuit.
This invention relates to non-volatile memory systems, specifically addressing the need for efficient status reporting during data read operations. The system includes a non-volatile memory device with a control circuit and a status register. The control circuit manages data read operations and communicates with an external controller. When the controller sends a first data read command, the control circuit transmits status data, including a busy bit indicating the operational state of the memory, to the controller via the status register. This ensures the controller receives immediate feedback on the memory's readiness, improving synchronization and reducing latency in read operations. The control circuit may also handle additional commands, such as write or erase operations, and manage internal memory operations like data transfer or error correction. The status register stores and provides access to the busy bit and other status flags, allowing the controller to monitor the memory's state efficiently. This mechanism enhances system performance by minimizing delays and ensuring timely status updates during read operations.
11. The non-volatile memory according to claim 10 , wherein the control circuit transmits the status data including the integrity verification bit from the status register to the controller when the second data read command send from the controller is received by the control circuit.
This invention relates to non-volatile memory systems, specifically addressing the need for efficient and reliable data integrity verification during read operations. The system includes a non-volatile memory device with a control circuit and a status register. The control circuit is configured to receive a first data read command from a controller and, in response, read data from a memory array. The control circuit then generates status data, which includes an integrity verification bit indicating whether the read data passed or failed an integrity check. This status data is stored in the status register. Upon receiving a second data read command from the controller, the control circuit transmits the status data, including the integrity verification bit, from the status register to the controller. This allows the controller to quickly determine the integrity of the read data without requiring additional processing or commands, improving efficiency and reliability in data retrieval operations. The system ensures that the controller can verify data integrity in a streamlined manner, reducing latency and computational overhead.
12. The non-volatile memory according to claim 11 , wherein the status data has 16 bits, first data read command is instructed to read a zero bit to a seventh bit in the status data, and the second data read command is instructed to an eighth bit to a fifteenth bit in the status data.
Non-volatile memory systems often require efficient access to status data, which may include information about memory operations, error conditions, or device health. A challenge arises when status data is large, as reading the entire data set can be inefficient, especially when only a portion of the data is needed. This invention addresses this issue by providing a non-volatile memory system with a segmented status data structure and corresponding read commands. The memory system includes a memory controller and a non-volatile memory device storing status data. The status data is divided into two segments: a first segment comprising the first eight bits (bits 0 to 7) and a second segment comprising the next eight bits (bits 8 to 15). The memory controller issues a first data read command to retrieve only the first segment (bits 0 to 7) and a second data read command to retrieve only the second segment (bits 8 to 15). This segmented approach allows selective reading of specific portions of the status data, improving efficiency by avoiding unnecessary reads of irrelevant data. The system may be implemented in flash memory, solid-state drives, or other non-volatile storage devices where partial status data access is beneficial.
13. The non-volatile memory according to claim 9 , wherein the busy bit is presented by logic “1” if the non-volatile memory is performing operations, and the busy bit is presented by logic “0” if the non-volatile memory does not perform any operation.
A non-volatile memory system includes a busy bit indicator to signal the operational status of the memory. The busy bit is set to logic "1" when the memory is actively performing operations, such as read, write, or erase operations, indicating that the memory is busy and unavailable for new commands. Conversely, the busy bit is set to logic "0" when the memory is idle and not performing any operations, indicating that it is ready to accept new commands. This busy bit provides a clear and efficient way for external systems or controllers to determine the availability of the memory, preventing conflicts or errors during concurrent access attempts. The busy bit may be part of a status register or a dedicated control interface within the memory device, ensuring real-time monitoring of the memory's operational state. This feature enhances system reliability and performance by enabling synchronized access and reducing the risk of data corruption or command collisions. The busy bit mechanism is particularly useful in embedded systems, solid-state storage devices, and other applications where non-volatile memory is frequently accessed.
14. The non-volatile memory according to claim 8 , wherein when the data value and the offset data value are different, the control circuit determines that the integrity of the memory cell to-be-inspected is defective.
This invention relates to non-volatile memory systems, specifically addressing the challenge of detecting memory cell integrity defects. The system includes a memory array with memory cells, a control circuit, and a data storage unit. The control circuit is configured to perform a data integrity check by reading a data value from a memory cell to-be-inspected and comparing it to an offset data value stored in the data storage unit. The offset data value is derived from the data value and represents an expected value under normal operating conditions. If the data value and the offset data value differ, the control circuit determines that the memory cell is defective, indicating a loss of data integrity. The system may also include a reference voltage generator to provide reference voltages for read operations and a voltage regulator to supply stable power to the memory array. The control circuit may further include a comparison circuit to compare the data value and the offset data value, and a determination circuit to assess the integrity of the memory cell based on the comparison result. This approach enables efficient and reliable detection of defective memory cells, ensuring data reliability in non-volatile memory systems.
15. The non-volatile memory according to claim 8 , further comprising: a voltage generator, configured to generate the read voltage and the preset voltage corresponding to the data value.
Non-volatile memory systems often face challenges in accurately reading stored data due to variations in memory cell characteristics and environmental conditions. This invention addresses these issues by incorporating a voltage generator that dynamically adjusts read voltages based on the data value being accessed. The memory system includes memory cells, a read circuit, and a voltage generator. The read circuit applies a read voltage to a selected memory cell to determine its stored data value. The voltage generator generates both the read voltage and a preset voltage, where the preset voltage is tailored to the specific data value being read. This ensures that the read operation is optimized for the particular data state, improving accuracy and reliability. The system may also include a control circuit that manages the read operation by selecting the appropriate read voltage and preset voltage based on the data value. By dynamically adjusting these voltages, the memory system compensates for variations in memory cell behavior, reducing errors and enhancing performance. This approach is particularly useful in high-density non-volatile memory devices where precise read operations are critical.
16. An electronic device, comprising: a non-volatile memory, comprising a memory array and a status register; and a controller, coupled to the non-volatile memory, wherein the controller sends a data integrity diagnosis command to the non-volatile memory, sends a first data read command to the non-volatile memory to obtain status data of the status register and to determine whether the non-volatile memory completes the data integrity diagnosis command according to a busy bit in the status data, when the data integrity diagnosis command is completed, the controller sends a second data read command to the non-volatile memory to obtain an integrity verification bit in the status data of the status register and to determine whether an integrity of a plurality of memory cells in the memory array is defective according to the integrity verification bit, wherein the busy bit is configured to indicate whether a memory data integrity inspection is being performed on the non-volatile memory, wherein the non-volatile memory, when receiving the data integrity diagnosis command, obtains a threshold voltage of at least one memory cell to-be-inspected in the non-volatile memory, determines a data value belonging to the at least one memory cell to-be-inspected by comparing a read voltage and the threshold voltage, wherein the data value has a first logic state when the threshold voltage is greater than the read voltage, and the data value has a second logic state when the threshold voltage is not greater than the read voltage, the non-volatile memory sets a preset voltage according to the data value when the data value belonging to the at least one memory cell to-be-inspected is determined, obtains an offset data value belonging to the at least one memory cell to-be-inspected by comparing the preset voltage and the threshold voltage of the at least one memory cell to-be-inspected, wherein the offset data value has the first logic state when the threshold voltage of the at least one memory cell to-be-inspected is greater than the preset voltage, and the offset data value has the second logic state when the threshold voltage of the at least one memory cell to-be-inspected is not greater than the preset voltage, determines whether the data value belonging to the at least one memory cell to-be-inspected and the offset data value belonging to the at least one memory cell to-be-inspected are the same, and determines that the integrity of the memory cell to-be-inspected is not defective in response to determining that the data value belonging to the at least one memory cell to-be-inspected and the offset data value belonging to the at least one memory cell to-be-inspected are the same.
This invention relates to an electronic device with a non-volatile memory that performs data integrity diagnosis. The device includes a non-volatile memory with a memory array and a status register, and a controller coupled to the memory. The controller sends a data integrity diagnosis command to the memory, which then inspects the integrity of memory cells by comparing threshold voltages of selected cells with a read voltage to determine their data values. The memory also sets a preset voltage based on these values and compares it with the threshold voltages again to obtain offset data values. If the original data values and offset data values match, the memory cell is deemed intact. The status register contains a busy bit to indicate ongoing diagnosis and an integrity verification bit to signal the result. The controller monitors the busy bit to check completion and then reads the integrity verification bit to assess memory cell integrity. This method ensures reliable detection of data integrity issues in non-volatile memory by verifying consistency between stored data and its offset values.
17. The electronic device according to claim 16 , wherein when the data value and the offset data value are different, the non-volatile memory determines that the integrity of the memory cell to-be-inspected is defective.
The invention relates to electronic devices with non-volatile memory, specifically addressing the challenge of detecting memory cell integrity issues. The system includes a non-volatile memory with memory cells, a controller, and a data processing unit. The controller reads a data value from a memory cell to be inspected and an offset data value from a neighboring memory cell. The data processing unit compares these values. If the data value and the offset data value differ, the non-volatile memory determines that the integrity of the inspected memory cell is defective. This approach leverages spatial redundancy by using neighboring cells to validate data integrity, improving reliability in non-volatile memory systems. The method involves reading data from adjacent cells, comparing the values, and flagging defects when discrepancies are found. This technique is particularly useful in detecting soft errors or degradation in memory cells without requiring additional error correction mechanisms. The system may also include a storage unit to store the data value and offset data value for further analysis or error handling. The invention enhances memory reliability by proactively identifying defective cells based on spatial correlations.
18. The electronic device according to claim 16 , the non-volatile memory further comprises: a voltage generator, configured to generate the read voltage and the preset voltage corresponding to the data value.
The invention relates to electronic devices with non-volatile memory, specifically addressing the challenge of efficiently managing read operations and data integrity in memory storage systems. The device includes a non-volatile memory that stores data values and generates read voltages and preset voltages corresponding to those values. The memory is configured to perform a read operation by applying a read voltage to a memory cell and comparing the resulting cell voltage to a preset voltage. If the cell voltage is higher than the preset voltage, the data value is determined to be a first value (e.g., '1'); otherwise, it is determined to be a second value (e.g., '0'). This comparison ensures accurate data retrieval by accounting for variations in cell voltage levels. The non-volatile memory further includes a voltage generator that produces the read and preset voltages based on the stored data values, enabling precise and reliable read operations. The system may also include a controller to manage these operations, ensuring efficient and error-free data access. This approach improves the reliability of data storage and retrieval in non-volatile memory systems by dynamically adjusting read parameters to match stored data values.
19. The electronic device according to claim 16 , wherein the first data read command is instructed to read parts of bits in the status data.
The invention relates to electronic devices with memory systems, specifically addressing the challenge of efficiently reading status data from memory to reduce power consumption and improve performance. The device includes a memory controller that generates a first data read command to read only parts of bits in the status data stored in a memory, rather than reading the entire status data. This selective reading minimizes unnecessary data transfers, conserving energy and reducing latency. The memory controller may also generate a second data read command to read the remaining parts of the status data if needed. The device further includes a memory interface that transmits the first data read command to the memory and receives the requested parts of the status data. The memory stores the status data, which may include information such as error flags, wear leveling indicators, or other metadata. By reading only the necessary portions of the status data, the device optimizes memory access operations, particularly in low-power or high-performance applications. The invention is applicable to various memory types, including flash memory, solid-state drives, and other non-volatile storage systems.
20. The electronic device according to claim 16 , wherein the second data read command is instructed to read another parts of bits in the status data, wherein the parts of bits in the status data are different form the another parts of bits in the status data.
This invention relates to electronic devices, particularly those involving memory or storage systems where status data is read to determine operational states. The problem addressed is efficiently accessing different portions of status data without redundant or unnecessary read operations, which can improve performance and reduce power consumption. The electronic device includes a memory controller configured to issue data read commands to a memory device. The memory device stores status data, which contains multiple parts of bits representing different operational states or conditions. The memory controller issues a first data read command to read a first part of the status data, and a second data read command to read a different part of the status data. The second data read command is specifically instructed to read a different set of bits in the status data than those read by the first command. This selective reading allows the device to access only the relevant portions of the status data, avoiding unnecessary reads of the entire status data set. The memory controller may use this selective reading to monitor or manage the memory device's state more efficiently, such as checking error conditions, readiness, or other operational parameters. The invention improves efficiency by reducing the number of read operations and the amount of data transferred, which is particularly beneficial in low-power or high-performance applications.
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September 1, 2020
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