Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A driving circuit, comprising: an input module connected to a cascaded signal input terminal, a first clock signal terminal, a low level terminal, a first node and a third node, configured to make a voltage of the first node be same as a voltage of the low level terminal, and make a voltage of the third node be same as a voltage of the cascaded signal input terminal according to a first clock signal at the first clock signal terminal; a first control module connected to the third node, a fourth node and a second clock signal terminal, configured to make a voltage of the fourth node be same as a voltage of the second clock signal terminal according to the voltage of the third node; a second control module connected to the fourth node, the first node and a high level terminal, configured to make the voltage of the first node be same as a voltage of the high level terminal according to the voltage of the fourth node; a third control module connected to the low level terminal, the third node and a second node, making a voltage of the second node be same as the voltage of the third node according to the voltage of the low level terminal; an output module connected to the second node, the second clock signal terminal and an output signal terminal, configured to output a second clock signal at the second clock signal terminal via the output signal terminal according to the voltage of the second node; a reset module connected to the first node, the high level terminal and the output signal terminal, configured to make a voltage of the output signal terminal be same as the voltage of the high level terminal according to the voltage of the first node; wherein the input module comprises: a first transistor comprising a first terminal connected to the low level terminal, a second terminal connected to the first node, and a gate connected to the first clock signal terminal; a second transistor comprising a first terminal connected to the cascaded signal input terminal, a second terminal connected to the third node, and a gate connected to the first clock signal terminal; wherein the first control module comprises a third transistor that comprises a first terminal connected to the second clock signal terminal, a second terminal connected to the fourth node, and a gate connected to the third node; wherein the second control module comprises: a fourth transistor comprising a first terminal connected to the high level terminal, a second terminal connected to the first node, and a gate connected to the fourth node; a first capacitor comprising a first electrode connected to the high level terminal, and a second electrode connected to the fourth node.
A driving circuit is designed to control signal transmission in electronic systems, particularly for cascaded signal processing. The circuit addresses the need for precise voltage control and signal synchronization in integrated circuits, ensuring reliable signal propagation while minimizing power consumption and signal distortion. The circuit includes multiple interconnected modules that regulate voltage levels at various nodes based on input signals and clock pulses. An input module receives a cascaded signal and a first clock signal, setting the voltage of a first node to a low level and the voltage of a third node to the cascaded signal level. A first control module then adjusts the voltage of a fourth node based on the third node's voltage, while a second control module sets the first node's voltage to a high level using a transistor and a capacitor. A third control module ensures the second node's voltage matches the third node's voltage. An output module transmits a second clock signal through an output terminal based on the second node's voltage. A reset module resets the output signal to a high level when triggered by the first node's voltage. The circuit employs transistors and capacitors to achieve precise voltage switching, ensuring efficient signal processing and synchronization in cascaded systems.
2. The driving circuit of claim 1 , wherein the first capacitor is a variable capacitor.
A driving circuit for an electronic device includes a variable capacitor that adjusts its capacitance to regulate voltage or current in the circuit. The variable capacitor dynamically modifies its capacitance value in response to changes in operating conditions, such as input voltage fluctuations or load variations, to maintain stable performance. This adjustment ensures consistent power delivery, reduces voltage ripple, and improves efficiency in applications like power supplies, amplifiers, or signal processing circuits. The variable capacitor may be implemented using semiconductor-based components, such as varactors or digitally tunable capacitors, allowing precise control over capacitance. By integrating this variable capacitor, the driving circuit can adapt to varying loads or environmental conditions without requiring additional external components, simplifying design and reducing cost. The technology addresses challenges in maintaining stable operation in dynamic electronic systems where fixed capacitors cannot adequately compensate for changing conditions.
3. The driving circuit of claim 1 , wherein the third control module comprises: a fifth transistor comprising a first terminal connected to the third node, a second terminal connected to the second node, and a gate connected to the low level terminal.
A driving circuit for electronic devices, particularly for controlling current flow in display panels or similar applications, addresses the challenge of efficiently managing signal transmission and power consumption. The circuit includes multiple transistors and control modules to regulate voltage levels and current paths. A third control module within the circuit features a fifth transistor with a first terminal connected to a third node, a second terminal connected to a second node, and a gate connected to a low-level terminal. This configuration ensures that the fifth transistor operates in response to a low-level signal, enabling precise control over current flow between the third and second nodes. The third control module, along with other components, helps stabilize voltage levels and prevent unwanted current leakage, improving the circuit's efficiency and reliability. The overall design focuses on optimizing signal integrity and power management in high-performance electronic systems.
4. The driving circuit of claim 1 , wherein the output module comprises: a sixth transistor comprising a first terminal connected to the second clock signal terminal, a second terminal connected to the output signal terminal, and a gate connected to the second node; a third capacitor comprising a first electrode connected to the second node, a second electrode connected to the output signal terminal.
This invention relates to a driving circuit for electronic displays, specifically addressing the need for stable and efficient signal output in display driver circuits. The circuit includes an output module designed to generate a reliable output signal using clock signals and control nodes. The output module features a sixth transistor and a third capacitor. The sixth transistor has a first terminal connected to a second clock signal terminal, a second terminal connected to an output signal terminal, and a gate connected to a second node. The third capacitor has a first electrode connected to the second node and a second electrode connected to the output signal terminal. This configuration ensures that the output signal is synchronized with the clock signal while maintaining stability through capacitive coupling. The circuit likely forms part of a larger shift register or gate driver, where precise timing and signal integrity are critical for proper display operation. The use of transistors and capacitors in this arrangement helps minimize signal distortion and power consumption, addressing common challenges in display driver design. The invention focuses on improving the reliability and efficiency of signal transmission in display panels, particularly in applications requiring high-resolution or high-refresh-rate displays.
5. The driving circuit of claim 1 , wherein the reset module comprises: a seventh transistor comprising a first terminal connected to the high level terminal, a second terminal connected to the output signal terminal, and a gate connected to the first node; a second capacitor comprising a first electrode connected to the high level terminal, and a second electrode of the second capacitor connects the first node.
This invention relates to a driving circuit for a display device, specifically addressing the need for stable and reliable signal output in pixel circuits. The circuit includes a reset module designed to reset the output signal terminal to a high level voltage during a reset phase, ensuring proper initialization of the pixel circuit before active operation. The reset module comprises a seventh transistor and a second capacitor. The seventh transistor has its first terminal connected to a high level terminal, its second terminal connected to the output signal terminal, and its gate connected to a first node. The second capacitor has its first electrode connected to the high level terminal and its second electrode connected to the first node. During the reset phase, the seventh transistor is activated, pulling the output signal terminal to the high level voltage, while the second capacitor stores this voltage at the first node, maintaining the reset state until the next phase. This design ensures that the output signal terminal is properly initialized, preventing signal distortion and improving display uniformity. The circuit is particularly useful in active matrix organic light-emitting diode (AMOLED) displays, where precise control of pixel driving is critical for image quality. The reset module's configuration minimizes leakage and enhances stability, addressing common issues in conventional driving circuits.
6. A driving circuit, comprising: an input module connected to a cascaded signal input terminal, a first clock signal terminal, a low level terminal, a first node and a third node, configured to make a voltage of the first node be same as a voltage of the low level terminal, and make a voltage of the third node be same as a voltage of the cascaded signal input terminal according to a first clock signal at the first clock signal terminal; a first control module connected to the third node, a fourth node and a second clock signal terminal, configured to make a voltage of the fourth node be same as a voltage of the second clock signal terminal according to the voltage of the third node; a second control module connected to the fourth node, the first node and a high level terminal, configured to make the voltage of the first node be same as a voltage of the high level terminal according to the voltage of the fourth node; a third control module connected to the low level terminal, the third node and a second node, making a voltage of the second node be same as the voltage of the third node according to the voltage of the low level terminal; an output module connected to the second node, the second clock signal terminal and an output signal terminal, configured to output a second clock signal at the second clock signal terminal via the output signal terminal according to the voltage of the second node; a reset module connected to the first node, the high level terminal and the output signal terminal, configured to make a voltage of the output signal terminal be same as the voltage of the high level terminal according to the voltage of the first node; wherein the second control module comprises: a fourth transistor comprising a first terminal connected to the high level terminal, a second terminal connected to the first node, and a gate of the fourth transistor connected to the fourth node; a first capacitor comprising a first electrode connected to the high level terminal, and a second electrode connected to the fourth node.
The invention relates to a driving circuit for signal processing, particularly in display technologies where precise timing and signal propagation are critical. The circuit addresses the need for efficient signal transmission and control in cascaded systems, ensuring accurate timing and minimizing signal distortion. The driving circuit includes multiple interconnected modules that work together to process and output signals based on clock inputs and control voltages. An input module receives a cascaded signal and a first clock signal, distributing voltages to a first node and a third node. The first control module then uses the voltage at the third node to control the voltage at a fourth node based on a second clock signal. A second control module, which includes a transistor and a capacitor, adjusts the voltage at the first node to match a high-level voltage when triggered by the fourth node's voltage. A third control module ensures a second node's voltage mirrors the third node's voltage, while an output module uses the second node's voltage to output the second clock signal. A reset module resets the output signal to a high-level voltage when the first node's voltage changes. The circuit's design ensures synchronized signal propagation and stable output, making it suitable for applications requiring precise timing control, such as shift registers in display drivers. The use of transistors and capacitors in the control modules enables efficient voltage switching and signal isolation.
7. The driving circuit of claim 6 , wherein the input module comprises: a first transistor comprising a first terminal connected to the low level terminal, a second terminal connected to the first node, and a gate connected to the first clock signal terminal; a second transistor comprising a first terminal connected to the cascaded signal input terminal, a second terminal connected to the third node, and a gate connected to the first clock signal terminal.
This invention relates to a driving circuit for electronic devices, specifically addressing signal transmission and control in integrated circuits. The circuit includes an input module designed to manage signal input and clock synchronization, ensuring reliable data transfer and timing control. The input module comprises two transistors. The first transistor connects a low-level terminal to a first node, with its gate controlled by a first clock signal. This transistor acts as a switch, pulling the first node to a low voltage level when the clock signal is active. The second transistor connects a cascaded signal input terminal to a third node, also controlled by the first clock signal. This transistor enables the transfer of input signals to the third node when the clock signal is active, facilitating synchronized data transmission. The circuit ensures proper signal isolation and timing alignment, improving the efficiency and accuracy of signal processing in integrated circuits. The transistors operate in response to the clock signal, ensuring that the input signals are correctly routed and controlled, which is critical for applications requiring precise timing and signal integrity.
8. The driving circuit of claim 6 , wherein the first control module comprises: a third transistor comprising a first terminal connected to the second clock signal terminal, a second terminal connected to the fourth node, and a gate connected to the third node.
A driving circuit for electronic displays, particularly for controlling pixel elements in active-matrix organic light-emitting diode (AMOLED) displays, addresses the challenge of achieving stable and efficient current driving to maintain uniform brightness and extend device lifespan. The circuit includes a first control module that regulates the flow of current to a pixel element based on input signals. This module incorporates a third transistor with a first terminal connected to a second clock signal terminal, a second terminal connected to a fourth node, and a gate connected to a third node. The third transistor acts as a switch, controlled by the voltage at the third node, to selectively pass or block the clock signal to the fourth node. This configuration ensures precise timing and synchronization of the driving signals, enabling accurate control of the pixel's emission current. The circuit also includes additional transistors and nodes that work together to stabilize the driving current, compensate for variations in transistor characteristics, and minimize power consumption. By integrating these components, the driving circuit enhances display performance, reduces flicker, and improves overall efficiency in AMOLED displays.
9. The driving circuit of claim 6 , wherein the first capacitor is a variable capacitor.
A driving circuit for electronic devices, particularly for controlling light-emitting elements such as LEDs, addresses the challenge of efficiently managing power and signal integrity in high-frequency or variable-load applications. The circuit includes a first capacitor connected to a switching element, which regulates current flow to the light-emitting element. The first capacitor is a variable capacitor, allowing dynamic adjustment of capacitance to optimize performance under different operating conditions. This adjustability enhances stability, reduces power loss, and improves response time in applications where load characteristics or environmental factors vary. The switching element, typically a transistor, controls the on/off states of the circuit, while the variable capacitor fine-tunes the circuit's impedance or timing characteristics. Additional components, such as a second capacitor or a control circuit, may further refine the circuit's behavior, ensuring consistent output despite fluctuations in input voltage or load demand. The variable capacitor's adaptability makes the driving circuit suitable for applications requiring precise control, such as display backlighting, automotive lighting, or industrial automation, where efficiency and reliability are critical.
10. The driving circuit of claim 6 , wherein the third control module comprises: a fifth transistor comprising a first terminal connected to the third node, a second terminal connected to the second node, and a gate connected to the low level terminal.
A driving circuit for electronic devices, particularly for display panels, addresses the challenge of efficiently controlling signal transmission and voltage regulation in integrated circuits. The circuit includes multiple transistors and control modules to manage signal paths and voltage levels. A third control module within the circuit regulates the flow of electrical signals between nodes to ensure proper operation. This module contains a fifth transistor with its first terminal connected to a third node, its second terminal connected to a second node, and its gate connected to a low-level terminal. The transistor acts as a switch, enabling or disabling the connection between the nodes based on the voltage level at the gate. This configuration ensures stable signal transmission and prevents voltage fluctuations, improving the reliability and performance of the driving circuit. The circuit is designed to handle high-frequency signals and maintain precise voltage levels, making it suitable for advanced display technologies and other high-speed electronic applications. The transistor's placement and connections optimize signal integrity and reduce power consumption, addressing common issues in integrated circuit design.
11. The driving circuit of claim 6 , wherein the output module comprises: a sixth transistor comprising a first terminal connected to the second clock signal terminal, a second terminal connected to the output signal terminal, and a gate connected to the second node; a third capacitor comprising a first electrode connected to the second node, and a second electrode connected to the output signal terminal.
This invention relates to a driving circuit for electronic displays, specifically addressing the need for stable and efficient signal output in shift register circuits used in display panels. The circuit includes an output module designed to enhance signal integrity and reduce power consumption. The output module features a sixth transistor and a third capacitor. The sixth transistor has a first terminal connected to a second clock signal terminal, a second terminal connected to an output signal terminal, and a gate connected to a second node. The third capacitor has a first electrode connected to the second node and a second electrode connected to the output signal terminal. This configuration ensures that the output signal is driven by the clock signal while maintaining synchronization with the internal node voltage, improving signal stability and reducing leakage current. The circuit is particularly useful in large-area displays where precise timing and low power consumption are critical. The output module's design minimizes signal distortion and enhances the overall performance of the shift register, making it suitable for high-resolution and high-refresh-rate display applications.
12. The driving circuit of claim 6 , wherein the reset module comprises: a seventh transistor comprising a first terminal connected to the high level terminal, a second terminal connected to the output signal terminal, and a gate connected to the first node; a second capacitor comprising a first electrode connected to the high level terminal, and a second electrode connected to the first node.
This invention relates to a driving circuit for a display device, specifically addressing the need for stable and efficient signal control in pixel circuits. The circuit includes a reset module designed to initialize and stabilize the voltage at a first node, which is critical for proper pixel operation. The reset module comprises a seventh transistor and a second capacitor. The seventh transistor has a first terminal connected to a high-level voltage terminal, a second terminal connected to an output signal terminal, and a gate connected to the first node. The second capacitor has a first electrode connected to the high-level voltage terminal and a second electrode connected to the first node. During operation, the reset module ensures that the first node is reset to a predetermined voltage level, preventing signal distortion and improving display uniformity. The transistor and capacitor work together to maintain stable voltage conditions, enhancing the reliability of the driving circuit. This design is particularly useful in active-matrix organic light-emitting diode (AMOLED) displays, where precise voltage control is essential for consistent brightness and color accuracy. The reset module's configuration minimizes leakage current and reduces power consumption, making it suitable for high-resolution and low-power display applications.
13. A driving circuit, comprising: a first transistor comprising a first terminal connected to the low level terminal, a second terminal connected to the first node, and a gate connected to the first clock signal terminal; a second transistor comprising a first terminal connected to the cascaded signal input terminal, a second terminal connected to the third node, and a gate connected to the first clock signal terminal; a third transistor comprising a first terminal connected to the second clock signal terminal, a second terminal connected to the fourth node, and a gate connected to the third node; a fourth transistor comprising a first terminal connected to the high level terminal, a second terminal connected to the first node, and a gate connected to the fourth node; a first capacitor comprising a first electrode connected to the high level terminal, and a second electrode connected to the fourth node; a fifth transistor comprising a first terminal connected to the third node, a second terminal connected to the second node, and a gate connected to the low level terminal; a sixth transistor comprising a first terminal connected to the second clock signal terminal, a second terminal connected to the output signal terminal, and a gate of the sixth transistor connects the second node; a third capacitor comprising a first electrode connected to the second node, and a second electrode connected to the output signal terminal; a seventh transistor comprising a first terminal connected to the high level terminal, a second terminal connected to the output signal terminal, and a gate connected to the first node; a second capacitor comprising a first electrode connected to the high level terminal, and a second electrode connected to the first node.
This invention relates to a driving circuit for electronic devices, particularly for controlling output signals in response to clock signals. The circuit addresses the need for efficient signal processing with minimal power consumption and improved stability. The driving circuit includes multiple transistors and capacitors configured to manage signal flow and timing. A first transistor connects a low-level terminal to a first node and is controlled by a first clock signal. A second transistor connects a cascaded signal input to a third node, also controlled by the first clock signal. A third transistor links a second clock signal terminal to a fourth node and is controlled by the third node. A fourth transistor connects a high-level terminal to the first node and is controlled by the fourth node. A first capacitor is connected between the high-level terminal and the fourth node. A fifth transistor connects the third node to a second node and is controlled by the low-level terminal. A sixth transistor connects the second clock signal terminal to an output signal terminal and is controlled by the second node. A third capacitor is connected between the second node and the output signal terminal. A seventh transistor connects the high-level terminal to the output signal terminal and is controlled by the first node. A second capacitor is connected between the high-level terminal and the first node. The circuit ensures precise timing and signal stability by coordinating the interactions between these components, enabling efficient signal amplification and output control.
Unknown
September 15, 2020
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