Driving Circuit

1. A driving circuit, comprising: an input module connected to a cascaded signal input terminal, a first clock signal terminal, a low level terminal, a first node and a third node, configured to make a voltage of the first node be same as a voltage of the low level terminal, and make a voltage of the third node be same as a voltage of the cascaded signal input terminal according to a first clock signal at the first clock signal terminal; a first control module connected to the third node, a fourth node and a second clock signal terminal, configured to make a voltage of the fourth node be same as a voltage of the second clock signal terminal according to the voltage of the third node; a second control module connected to the fourth node, the first node and a high level terminal, configured to make the voltage of the first node be same as a voltage of the high level terminal according to the voltage of the fourth node; a third control module connected to the low level terminal, the third node and a second node, making a voltage of the second node be same as the voltage of the third node according to the voltage of the low level terminal; an output module connected to the second node, the second clock signal terminal and an output signal terminal, configured to output a second clock signal at the second clock signal terminal via the output signal terminal according to the voltage of the second node; a reset module connected to the first node, the high level terminal and the output signal terminal, configured to make a voltage of the output signal terminal be same as the voltage of the high level terminal according to the voltage of the first node; wherein the input module comprises: a first transistor comprising a first terminal connected to the low level terminal, a second terminal connected to the first node, and a gate connected to the first clock signal terminal; a second transistor comprising a first terminal connected to the cascaded signal input terminal, a second terminal connected to the third node, and a gate connected to the first clock signal terminal; wherein the first control module comprises a third transistor that comprises a first terminal connected to the second clock signal terminal, a second terminal connected to the fourth node, and a gate connected to the third node; wherein the second control module comprises: a fourth transistor comprising a first terminal connected to the high level terminal, a second terminal connected to the first node, and a gate connected to the fourth node; a first capacitor comprising a first electrode connected to the high level terminal, and a second electrode connected to the fourth node.

2. The driving circuit of claim 1 , wherein the first capacitor is a variable capacitor.

3. The driving circuit of claim 1 , wherein the third control module comprises: a fifth transistor comprising a first terminal connected to the third node, a second terminal connected to the second node, and a gate connected to the low level terminal.

4. The driving circuit of claim 1 , wherein the output module comprises: a sixth transistor comprising a first terminal connected to the second clock signal terminal, a second terminal connected to the output signal terminal, and a gate connected to the second node; a third capacitor comprising a first electrode connected to the second node, a second electrode connected to the output signal terminal.

5. The driving circuit of claim 1 , wherein the reset module comprises: a seventh transistor comprising a first terminal connected to the high level terminal, a second terminal connected to the output signal terminal, and a gate connected to the first node; a second capacitor comprising a first electrode connected to the high level terminal, and a second electrode of the second capacitor connects the first node.

6. A driving circuit, comprising: an input module connected to a cascaded signal input terminal, a first clock signal terminal, a low level terminal, a first node and a third node, configured to make a voltage of the first node be same as a voltage of the low level terminal, and make a voltage of the third node be same as a voltage of the cascaded signal input terminal according to a first clock signal at the first clock signal terminal; a first control module connected to the third node, a fourth node and a second clock signal terminal, configured to make a voltage of the fourth node be same as a voltage of the second clock signal terminal according to the voltage of the third node; a second control module connected to the fourth node, the first node and a high level terminal, configured to make the voltage of the first node be same as a voltage of the high level terminal according to the voltage of the fourth node; a third control module connected to the low level terminal, the third node and a second node, making a voltage of the second node be same as the voltage of the third node according to the voltage of the low level terminal; an output module connected to the second node, the second clock signal terminal and an output signal terminal, configured to output a second clock signal at the second clock signal terminal via the output signal terminal according to the voltage of the second node; a reset module connected to the first node, the high level terminal and the output signal terminal, configured to make a voltage of the output signal terminal be same as the voltage of the high level terminal according to the voltage of the first node; wherein the second control module comprises: a fourth transistor comprising a first terminal connected to the high level terminal, a second terminal connected to the first node, and a gate of the fourth transistor connected to the fourth node; a first capacitor comprising a first electrode connected to the high level terminal, and a second electrode connected to the fourth node.

7. The driving circuit of claim 6 , wherein the input module comprises: a first transistor comprising a first terminal connected to the low level terminal, a second terminal connected to the first node, and a gate connected to the first clock signal terminal; a second transistor comprising a first terminal connected to the cascaded signal input terminal, a second terminal connected to the third node, and a gate connected to the first clock signal terminal.

8. The driving circuit of claim 6 , wherein the first control module comprises: a third transistor comprising a first terminal connected to the second clock signal terminal, a second terminal connected to the fourth node, and a gate connected to the third node.

9. The driving circuit of claim 6 , wherein the first capacitor is a variable capacitor.

10. The driving circuit of claim 6 , wherein the third control module comprises: a fifth transistor comprising a first terminal connected to the third node, a second terminal connected to the second node, and a gate connected to the low level terminal.

11. The driving circuit of claim 6 , wherein the output module comprises: a sixth transistor comprising a first terminal connected to the second clock signal terminal, a second terminal connected to the output signal terminal, and a gate connected to the second node; a third capacitor comprising a first electrode connected to the second node, and a second electrode connected to the output signal terminal.

12. The driving circuit of claim 6 , wherein the reset module comprises: a seventh transistor comprising a first terminal connected to the high level terminal, a second terminal connected to the output signal terminal, and a gate connected to the first node; a second capacitor comprising a first electrode connected to the high level terminal, and a second electrode connected to the first node.

13. A driving circuit, comprising: a first transistor comprising a first terminal connected to the low level terminal, a second terminal connected to the first node, and a gate connected to the first clock signal terminal; a second transistor comprising a first terminal connected to the cascaded signal input terminal, a second terminal connected to the third node, and a gate connected to the first clock signal terminal; a third transistor comprising a first terminal connected to the second clock signal terminal, a second terminal connected to the fourth node, and a gate connected to the third node; a fourth transistor comprising a first terminal connected to the high level terminal, a second terminal connected to the first node, and a gate connected to the fourth node; a first capacitor comprising a first electrode connected to the high level terminal, and a second electrode connected to the fourth node; a fifth transistor comprising a first terminal connected to the third node, a second terminal connected to the second node, and a gate connected to the low level terminal; a sixth transistor comprising a first terminal connected to the second clock signal terminal, a second terminal connected to the output signal terminal, and a gate of the sixth transistor connects the second node; a third capacitor comprising a first electrode connected to the second node, and a second electrode connected to the output signal terminal; a seventh transistor comprising a first terminal connected to the high level terminal, a second terminal connected to the output signal terminal, and a gate connected to the first node; a second capacitor comprising a first electrode connected to the high level terminal, and a second electrode connected to the first node.