Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A method of operating a multi-threaded processor comprising: fetching a plurality of instructions from a program by a first thread starting at a first program counter, the first thread using a first register bank; fetching a plurality of instructions from the program by a second thread starting at the first program counter, the second thread using a second register bank in response to the first thread stalling at a point in the program or reaching a predefined synchronization point in the program, wherein the predefined synchronization point is a memory write; comparing contents of the first and second register banks in response to the second thread reaching the point in the program where the first thread stalled or reached the predefined synchronization point; and triggering a further plurality of instructions from the program by one of the first and second threads followed by a further plurality of instructions by the other of the first and second threads in response to determining that the contents match.
This invention relates to multi-threaded processor operation, specifically addressing performance optimization by reducing thread stalling and synchronization overhead. The method involves two threads executing the same program concurrently but independently, each using separate register banks. The first thread begins execution at a specified program counter, while the second thread starts at the same point but only activates if the first thread stalls or reaches a predefined synchronization point, such as a memory write. When the second thread reaches the point where the first thread stalled or the synchronization point, the contents of both register banks are compared. If they match, execution continues with one thread followed by the other, ensuring consistency while minimizing delays. This approach improves efficiency by allowing the second thread to proceed when the first is blocked, then synchronizing results to maintain correctness. The technique is particularly useful in scenarios where threads frequently stall due to memory access or other delays, as it enables parallel progress without requiring complex synchronization mechanisms.
2. The method of claim 1 wherein the triggering comprises beginning execution of the further plurality of instructions from the program.
This invention relates to a method for executing instructions in a computing system, specifically addressing the challenge of efficiently triggering the execution of additional program instructions. The method involves a system that monitors the execution of a primary set of instructions from a program. When a specific condition is detected during this execution, the system triggers the initiation of a further set of instructions from the same program. The triggering mechanism ensures that the additional instructions are executed in a controlled and timely manner, improving system performance and resource utilization. The method may include steps such as detecting a predefined event or state during the execution of the primary instructions, validating the detected condition, and then initiating the execution of the further instructions. This approach allows for dynamic and responsive program execution, adapting to runtime conditions without manual intervention. The invention is particularly useful in environments where program behavior must be adjusted based on real-time events or system states, such as in real-time systems, embedded applications, or adaptive software frameworks. By automating the triggering of additional instructions, the method enhances efficiency and reduces the need for static, preconfigured execution paths.
3. The method of claim 1 wherein the triggering comprises fetching the further plurality of instructions from the program.
A system and method for optimizing program execution involves dynamically triggering the retrieval of additional instructions from a program during runtime to enhance performance. The method addresses inefficiencies in traditional execution models where programs rely on preloaded or statically determined instruction sets, which may not adapt to runtime conditions. The system monitors execution flow and identifies points where additional instructions are needed to improve efficiency, such as optimizing resource usage or reducing latency. When a triggering condition is met, the system fetches a further set of instructions from the program, dynamically integrating them into the execution pipeline. This allows the program to adapt to changing conditions, such as varying workloads or system states, without requiring manual intervention or recompilation. The method ensures seamless integration of the fetched instructions, maintaining program correctness while improving performance. The approach is particularly useful in environments where execution conditions are unpredictable or highly variable, such as real-time systems or resource-constrained devices. By dynamically adjusting the instruction set, the system achieves better resource utilization and faster execution times compared to static approaches.
4. The method of claim 1 wherein the comparing of the contents of the first and second register banks comprises comparing a subset of the contents.
The invention relates to a method for comparing contents of register banks in a computing system, addressing the problem of efficiently verifying data consistency between multiple register banks without excessive computational overhead. The method involves comparing the contents of a first register bank and a second register bank, where the comparison is performed on a subset of the contents rather than the entire contents. This selective comparison reduces the computational resources required while still ensuring data integrity. The subset may be determined based on predefined criteria, such as specific memory addresses, data types, or other relevant parameters. The method may also include steps for initializing the register banks, storing data in the register banks, and performing the comparison operation. The selective comparison approach is particularly useful in systems where full comparisons are impractical due to performance constraints or where partial verification is sufficient for the intended application. The invention aims to optimize the comparison process by focusing on critical data subsets, thereby improving efficiency without compromising reliability.
5. The method of claim 1 further comprising allowing the memory write to complete before triggering a further plurality of instructions from the program by one of the first and second threads followed by a further plurality of instructions by the other of the first and second threads in response to determining that the contents match.
This invention relates to a method for managing memory writes in a multi-threaded computing environment to ensure data consistency. The problem addressed is the potential for race conditions or data corruption when multiple threads attempt to write to the same memory location simultaneously. The method involves comparing the contents of a memory location before and after a write operation to determine if the write was successful. If the contents match, indicating no interference from other threads, the method allows the write to complete before proceeding with subsequent instructions from both threads in an interleaved manner. This ensures that the memory state remains consistent and prevents conflicts between concurrent writes. The method may also involve tracking the memory location to detect changes and validating the write operation by verifying the expected data was written. The approach is particularly useful in systems where thread synchronization mechanisms like locks are undesirable due to performance overhead or complexity. By dynamically checking memory consistency, the method enables efficient and safe concurrent access to shared memory resources.
6. The method of claim 1 further comprising comparing write data and write addresses of memory writes of the first and second threads.
A system and method for managing memory access in a multi-threaded computing environment addresses the challenge of ensuring data consistency and preventing conflicts when multiple threads attempt to write to the same memory locations. The invention involves monitoring memory write operations from at least two threads executing concurrently on a processor. Each thread generates write data and corresponding write addresses, which are tracked to detect potential conflicts. The method further includes comparing the write data and write addresses of the memory writes from the first and second threads to identify overlapping or conflicting access patterns. This comparison helps prevent data corruption by ensuring that writes from different threads do not interfere with each other. The system may also include mechanisms to synchronize or prioritize memory access based on the comparison results, ensuring thread safety and maintaining system stability. The invention is particularly useful in high-performance computing, real-time systems, and applications where multiple threads frequently access shared memory resources. By detecting and resolving conflicts early, the system improves efficiency and reliability in multi-threaded environments.
7. The method of claim 6 wherein the triggering a further plurality of instructions from the program by one of the first and second threads followed by a further plurality of instructions by the other of the first and second threads in response to determining that the contents match only occurs when the comparing write data and write addresses of memory writes of the first and second threads produces a match.
This invention relates to a method for managing memory access in a multi-threaded computing environment to prevent race conditions. The problem addressed is ensuring thread safety when multiple threads attempt to write to the same memory location, which can lead to data corruption or inconsistent states. The method involves comparing the write data and write addresses of memory writes from two threads. If the contents of the writes match, the method triggers a sequence of instructions from one thread followed by another sequence from the other thread, but only if the comparison of write data and addresses produces a match. This ensures that conflicting writes are handled in a controlled manner, preventing race conditions. The method includes monitoring memory writes from both threads, comparing their data and addresses, and conditionally executing subsequent instructions based on the comparison result. The approach ensures that only matching writes trigger the sequential execution of instructions, maintaining data integrity in concurrent memory operations.
8. The method of claim 1 wherein the predefined synchronization point is a cache miss.
A method for optimizing data processing in a computing system involves detecting a predefined synchronization point during execution to trigger a synchronization operation. The synchronization point is specifically a cache miss, indicating when data requested by a processor is not found in the cache memory. Upon detecting this cache miss, the system performs a synchronization operation to ensure data consistency between different processing elements or memory levels. This synchronization may involve flushing pending operations, updating shared data, or coordinating between processors to maintain coherence. The method improves system performance by reducing unnecessary synchronization overhead while ensuring data integrity when critical events like cache misses occur. The approach is particularly useful in multi-core or distributed computing environments where efficient synchronization is essential for maintaining performance and correctness. The system may also include mechanisms to dynamically adjust synchronization frequency or conditions based on workload characteristics to further optimize efficiency.
9. The method of claim 8 further comprising storing data to be written as a result of an output of the first thread as an entry in a write buffer and updating a state associated with the entry in the write buffer to indicate that it has been written by the first thread.
This invention relates to data processing systems, specifically methods for managing data writes in a multi-threaded environment. The problem addressed is ensuring data consistency and synchronization when multiple threads attempt to write data simultaneously, which can lead to race conditions, data corruption, or inconsistent states. The method involves a system where a first thread generates data to be written to a storage medium. Instead of directly writing the data, the method stores the data as an entry in a write buffer. The write buffer acts as an intermediate storage layer that temporarily holds the data before it is committed to the storage medium. The method then updates a state associated with the entry in the write buffer to indicate that the first thread has successfully written the data to the buffer. This state update ensures that other threads or processes can track the completion of the write operation by the first thread, preventing conflicts or overwrites. Additionally, the method may involve a second thread that reads data from the write buffer. The second thread checks the state of the entries in the write buffer to determine which data has been written by the first thread and is ready for further processing or storage. This synchronization mechanism ensures that the second thread only accesses data that has been properly written by the first thread, maintaining data integrity. The write buffer and state tracking system provide a structured way to manage concurrent writes, reducing the risk of data corruption and ensuring that all threads operate on consistent data states. This approach is particularly useful in high-performance computing environments where multiple threads must coordinate their operations efficiently.
10. The method of claim 9 further comprising reading data from the entry in the write buffer instead of from a memory location or a cache in response to fetching a subsequent read instruction of the memory location by the first thread.
A method for optimizing memory access in a multi-threaded processing system addresses inefficiencies in data retrieval when multiple threads access shared memory locations. The method involves a write buffer that temporarily stores data written by a first thread to a memory location. When a second thread subsequently attempts to read from the same memory location, the system checks whether the data is available in the write buffer before accessing the memory or cache. If the data is found in the write buffer, it is read directly from there, reducing latency and improving performance by avoiding slower memory or cache accesses. This approach is particularly useful in systems where threads frequently access shared data, as it minimizes unnecessary memory or cache lookups. The method ensures data consistency by ensuring that the most recent write operation is reflected in subsequent reads, even if the data has not yet been committed to the main memory or cache. The write buffer acts as an intermediate storage layer, dynamically providing the latest data to reading threads while maintaining synchronization between concurrent operations. This technique enhances efficiency in multi-threaded environments by reducing contention for shared memory resources and accelerating data access times.
11. The method of claim 1 further comprising storing a current value of a program counter of the first thread in response to the first thread stalling at a point in the program or reaching a predefined synchronization point in the program.
A method for managing thread execution in a computing system involves tracking and storing the state of threads to optimize performance. The method addresses the problem of inefficient thread handling, particularly when threads stall or reach synchronization points, which can lead to wasted computational resources and delays. The method includes storing a current value of a program counter for a first thread when the thread stalls at a specific point in the program or reaches a predefined synchronization point. This stored value allows the system to later resume execution of the thread from the exact point where it stalled or synchronized, improving efficiency and reducing unnecessary processing. The method may also involve detecting when the first thread stalls or reaches a synchronization point, determining whether the thread should be paused or resumed, and managing the execution of other threads in the system to ensure optimal resource utilization. By tracking and storing thread states, the method ensures that computational resources are used effectively, minimizing idle time and improving overall system performance.
12. The method of claim 11 further comprising determining when the second thread reaches the point in the program where the first thread stalled or reached the predefined synchronization point based on when a program counter of the second thread equals the current value of the program counter that was stored.
This invention relates to thread synchronization in multi-threaded computing environments, specifically addressing the challenge of efficiently managing thread execution when one thread stalls or reaches a predefined synchronization point. The method involves monitoring the execution of multiple threads in a program, where a first thread may stall or reach a synchronization point, causing a delay in its execution. To mitigate this, the system stores the current program counter value of the first thread at the point of stalling or synchronization. A second thread, which may be executing concurrently, is then monitored to determine when its program counter matches the stored value of the first thread's program counter. This matching indicates that the second thread has reached the same point in the program where the first thread stalled or synchronized. The method ensures that the second thread can proceed or take appropriate action based on the synchronization state of the first thread, improving coordination between threads and preventing race conditions or deadlocks. The approach leverages program counter tracking to dynamically synchronize thread execution, enhancing efficiency and reliability in multi-threaded applications.
13. The method of claim 1 further comprising incrementing a first instruction counter for each instruction executed by the first thread after the first program counter.
A method for tracking instruction execution in a multi-threaded processing system addresses the challenge of monitoring and managing instruction flow in parallel processing environments. The method involves executing instructions from a first thread using a first program counter, where the first program counter is initialized to a starting address in a memory. As the first thread executes instructions, a first instruction counter is incremented for each instruction executed after the first program counter. This allows for precise tracking of instruction execution within the thread, enabling performance monitoring, debugging, or synchronization tasks. The method may also include similar tracking for a second thread, where a second program counter and a second instruction counter are used to monitor its execution independently. The counters provide a way to measure the progress of each thread, ensuring proper coordination and error detection in multi-threaded applications. This approach is particularly useful in systems where thread execution must be closely monitored to maintain efficiency and correctness.
14. The method of claim 13 further comprising storing a current value of a program counter of the first thread in response to the first thread stalling at a point in the program or reaching a predefined synchronization point in the program.
This invention relates to thread management in computing systems, specifically addressing the challenge of efficiently handling thread stalling or synchronization in multi-threaded environments. The method involves monitoring the execution of a first thread in a computing system to detect when the thread stalls at a specific point in the program or reaches a predefined synchronization point. Upon detection, the current value of the program counter for the first thread is stored. This stored value can later be used to resume execution of the thread from the exact point where it stalled or synchronized, improving efficiency and reducing unnecessary reprocessing. The method may also involve tracking the state of the first thread, such as its execution context or pending operations, to facilitate seamless resumption. Additionally, the system may manage multiple threads, where the stored program counter values and thread states are used to coordinate execution across threads, ensuring proper synchronization and avoiding conflicts. The technique is particularly useful in systems where threads frequently stall due to resource contention, external dependencies, or synchronization barriers, as it minimizes wasted computational effort and enhances overall system performance.
15. The method of claim 14 further comprising incrementing a second instruction counter for each instruction executed by the second thread after the first thread has stalled or reached the predefined synchronization point.
This invention relates to a method for tracking instruction execution in a multi-threaded processing system, particularly for monitoring thread synchronization and performance. The method addresses the challenge of efficiently managing and analyzing instruction execution across multiple threads, especially when threads stall or reach predefined synchronization points, which can disrupt performance and complicate debugging. The method involves executing a first thread and a second thread in parallel on a processor. A first instruction counter is incremented for each instruction executed by the first thread. When the first thread stalls or reaches a predefined synchronization point, a second instruction counter is incremented for each instruction executed by the second thread. This allows for separate tracking of instructions executed by the second thread before and after the first thread's stall or synchronization, providing detailed performance metrics and synchronization analysis. The method ensures accurate monitoring of thread execution, particularly in scenarios where threads must synchronize or when one thread stalls, which can impact overall system performance. By maintaining separate counters, the system can distinguish between instructions executed during normal operation and those executed after a synchronization event, aiding in debugging and optimization. The approach is useful in multi-core or multi-threaded environments where thread coordination is critical.
16. The method of claim 15 further comprising determining when the second thread reaches the point in the program where the first thread stalled or reached the predefined synchronization point based on a program counter of the second thread equaling the first program counter and the second instruction counter equaling the first instruction counter.
This invention relates to thread synchronization in parallel computing, specifically addressing the challenge of efficiently managing thread execution when one thread stalls or reaches a predefined synchronization point. The method involves monitoring the execution of multiple threads in a parallel computing environment to detect when a second thread reaches the same program state as a first thread that has stalled or reached a synchronization point. The system tracks the program counter and instruction counter of each thread to determine when the second thread matches the stalled or synchronized state of the first thread. This allows the system to coordinate thread execution, ensuring proper synchronization and avoiding race conditions or deadlocks. The method improves efficiency by dynamically adjusting thread execution based on real-time program state comparisons, reducing unnecessary delays and optimizing resource utilization. The solution is particularly useful in multi-threaded applications where precise synchronization is critical, such as in high-performance computing, real-time systems, and parallel processing environments.
17. The method of claim 15 wherein the first and second instruction counters are not incremented upon execution of a speculative instruction.
A method for managing instruction execution in a processor involves tracking instruction execution using first and second instruction counters. The counters are incremented upon execution of non-speculative instructions, allowing the processor to monitor and control instruction flow. The method includes determining whether an instruction is speculative, and if so, preventing the counters from incrementing. This ensures accurate tracking of committed instructions while avoiding miscounts due to speculative execution. The technique is particularly useful in out-of-order processors where speculative execution is common, helping maintain precise instruction ordering and state management. By selectively incrementing the counters only for non-speculative instructions, the method improves performance and reliability in complex processing environments. The approach may be integrated into a processor pipeline or a dedicated execution control unit, ensuring efficient handling of both speculative and non-speculative instructions. The method supports accurate program flow analysis, debugging, and performance monitoring by distinguishing between committed and speculative instructions.
18. The method of claim 17 further comprising incrementing a fourth instruction counter for each speculative instruction executed by an executing thread.
A method for tracking speculative instruction execution in a multi-threaded processor involves monitoring and counting instructions executed by multiple threads. The method includes maintaining separate counters for different types of instructions, such as committed, retired, and speculative instructions, to provide detailed performance metrics. A fourth counter is specifically used to track speculative instructions executed by each thread, allowing for precise analysis of speculative execution behavior. The method ensures accurate tracking by distinguishing between instructions that are committed, retired, or still speculative, enabling better performance optimization and debugging. The counters are updated dynamically as threads execute instructions, providing real-time insights into the processor's operation. This approach helps identify inefficiencies in speculative execution and improves overall system performance by reducing unnecessary speculative work. The method is particularly useful in high-performance computing environments where speculative execution plays a critical role in performance optimization.
19. The method of claim 18 further comprising adding a value of the fourth instruction counter to the first instruction counter if the first thread is the executing thread or to the second instruction counter if the second thread is the executing thread, based on correct branch prediction.
This invention relates to a method for managing instruction counters in a multi-threaded processor system to improve performance and accuracy in branch prediction. The method addresses the challenge of tracking instruction execution across multiple threads, particularly when branch predictions are made, to ensure correct synchronization and performance optimization. The method involves monitoring two threads executing on a processor, where each thread has an associated instruction counter. A fourth instruction counter is used to track the execution of instructions following a branch prediction. If the branch prediction is correct, the value of the fourth instruction counter is added to the instruction counter of the executing thread. This ensures that the instruction counters accurately reflect the sequence of executed instructions, even after a branch prediction. The method also includes determining whether the first or second thread is the executing thread and updating the corresponding instruction counter accordingly. This approach helps maintain precise instruction tracking, which is critical for performance monitoring, debugging, and optimizing multi-threaded processor operations. The method improves the accuracy of branch prediction feedback and ensures that instruction counters remain synchronized with actual execution flow, enhancing overall system efficiency.
20. The method of claim 19 further comprising adding a fifth instruction counter, wherein the fifth instruction counter is incremented for each instruction fetched by the second thread.
A method for managing instruction execution in a multi-threaded processor architecture addresses the challenge of tracking instruction progress in parallel processing environments. The method involves monitoring instruction execution across multiple threads to optimize performance and resource allocation. A first instruction counter tracks instructions fetched by a first thread, while a second instruction counter tracks instructions fetched by a second thread. A third instruction counter increments for each instruction executed by the first thread, and a fourth instruction counter increments for each instruction executed by the second thread. This allows the processor to distinguish between fetched and executed instructions for each thread, enabling efficient scheduling and conflict resolution. The method further includes a fifth instruction counter that increments for each instruction fetched by the second thread, providing additional granularity in tracking instruction flow. This counter helps identify bottlenecks or inefficiencies in instruction fetching for the second thread, allowing for dynamic adjustments to improve throughput. The system ensures accurate synchronization between instruction fetching and execution, reducing stalls and enhancing overall processor efficiency. The method is particularly useful in high-performance computing and real-time processing applications where precise instruction tracking is critical.
21. The method of claim 20 wherein an exception is raised based on the fifth instruction counter equaling a threshold value.
A system and method for monitoring and controlling instruction execution in a computing environment involves tracking instruction counters to detect and respond to specific execution conditions. The method includes maintaining multiple instruction counters, each associated with different types of instructions or execution paths. A fifth instruction counter is used to track a particular set of instructions or a specific execution scenario. When this counter reaches a predefined threshold value, an exception is triggered. This exception can be used to halt execution, log an error, or initiate a corrective action. The system may also include mechanisms to reset or adjust the counters based on external conditions or user-defined rules. The method ensures that instruction execution remains within safe or expected limits, preventing potential errors or security vulnerabilities. The threshold value can be dynamically adjusted to adapt to different operational scenarios or performance requirements. This approach is particularly useful in environments where precise control over instruction execution is necessary, such as in embedded systems, real-time processing, or security-critical applications.
22. The method of claim 21 further comprising incrementing the fifth instruction counter for each instruction fetched by the second thread, copying contents of a third register bank to the first and second register banks, triggering refetching of a plurality of instructions from the program by one or the first and second threads starting at the first program counter, and resetting the fifth instruction counter, based on determining that the fifth instruction counter equals a threshold value.
This invention relates to a method for managing instruction execution in a multi-threaded processor system, particularly addressing the need for efficient thread synchronization and register management. The method involves a processor executing instructions from a program using at least two threads, where each thread operates with its own program counter and instruction counter. The first thread fetches instructions from the program starting at a first program counter, while the second thread fetches instructions starting at a second program counter. The method includes incrementing a fifth instruction counter for each instruction fetched by the second thread. When the fifth instruction counter reaches a threshold value, the method copies the contents of a third register bank to both the first and second register banks, triggers a refetch of instructions from the program starting at the first program counter, and resets the fifth instruction counter. This ensures synchronized execution and register state consistency between threads, improving performance and reliability in multi-threaded environments. The method may also involve adjusting the first and second program counters based on the fetched instructions, further optimizing instruction flow and thread coordination.
23. The method of claim 1 further comprising enforcing a minimum time separation of S clock cycles between the first and second thread executing a same instruction from the same program, wherein S is a predefined, positive integer.
This invention relates to a method for managing thread execution in a computing system to prevent timing side-channel attacks. The problem addressed is the risk of information leakage through shared execution resources, where threads executing the same instruction from the same program could reveal sensitive data via timing variations. The method enforces a minimum time separation of S clock cycles between the first and second thread executing the same instruction from the same program, where S is a predefined, positive integer. This ensures that the execution of these threads is sufficiently spaced in time, mitigating the risk of timing-based side-channel attacks. The method may also include detecting when two threads are executing the same instruction from the same program and then enforcing the minimum time separation. The predefined value S can be adjusted based on system requirements or security policies to balance performance and security. This approach is particularly useful in multi-threaded environments where shared resources could otherwise be exploited to infer confidential information.
24. A multi-threaded processing apparatus comprising: a first register bank associated with a first thread; a second register bank associated with a second thread; and a multi-stage execution pipeline comprising: a scheduler implemented in hardware logic and arranged to cause a plurality of instructions from a program to be fetched by the first thread starting at a first program counter value and to cause a plurality of instructions from the same program to be fetched by the second thread starting at the first program counter in response to the first thread stalling or reaching a predefined synchronization point in the program, wherein the predefined synchronization point is a memory write; and comparison logic arranged to compare contents of the first and second register banks in response to determining that the second thread has caught up with the first thread, wherein in response to determining that the contents match, to trigger fetching of a next plurality of instructions from the program by one of the first and second threads followed by the other of the first and second threads.
This invention relates to multi-threaded processing systems designed to improve performance by efficiently handling thread stalling and synchronization. The problem addressed is the inefficiency in multi-threaded execution when one thread stalls, causing idle cycles in the processor pipeline. The solution involves a hardware-based scheduler that dynamically manages thread execution to minimize stalls and maintain pipeline efficiency. The apparatus includes two register banks, each associated with a separate thread, and a multi-stage execution pipeline. The scheduler, implemented in hardware logic, fetches instructions for the first thread starting at a specific program counter value. If the first thread stalls or reaches a predefined synchronization point (specifically a memory write operation), the scheduler initiates the second thread to fetch instructions from the same program counter value. This allows the second thread to proceed while the first thread is stalled, reducing idle cycles. When the second thread catches up with the first, comparison logic checks the contents of both register banks. If the register contents match, indicating synchronization, the system triggers the fetching of the next set of instructions. The threads then alternate fetching instructions, ensuring efficient pipeline utilization and maintaining execution continuity. This approach optimizes performance by dynamically balancing thread execution and minimizing stalls.
25. A computer program product embodied in a non-transitory computer readable medium for multi-threaded processor operation, the computer program product comprising code which causes one or more processors to perform operations of: fetching a plurality of instructions from a program by a first thread starting at a first program counter, the first thread using a first register bank; fetching a plurality of instructions from the program by a second thread starting at the first program counter, the second thread using a second register bank in response to the first thread stalling at a point in the program or reaching a predefined synchronization point in the program, wherein the predefined synchronization point is a memory write; comparing contents of the first and second register banks in response to the second thread reaching the point in the program where the first thread stalled or reached the predefined synchronization point; and triggering a further plurality of instructions from the program by one of the first and second threads followed by a further plurality of instructions by the other of the first and second threads in response to determining that the contents match.
This invention relates to multi-threaded processor operation, specifically addressing inefficiencies in thread execution when a primary thread stalls or reaches a synchronization point. The problem occurs when a single thread's progress is halted due to delays (e.g., memory access latency) or synchronization requirements, leading to underutilized processor resources. The solution involves a computer program product that enables a secondary thread to take over execution from the same program counter but using a separate register bank. When the primary thread stalls or reaches a predefined synchronization point (such as a memory write), the secondary thread begins executing instructions from the same starting point. Upon reaching the stall point or synchronization point, the contents of both register banks are compared. If they match, execution continues with alternating instruction fetches between the threads, effectively masking latency and improving processor efficiency. This approach leverages hardware multithreading to maintain progress during stalls while ensuring consistency through register bank comparison. The method avoids redundant work by validating register states before proceeding, ensuring correct program execution.
Unknown
September 22, 2020
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.