Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A system comprising: one or more processors of a machine; and a computer storage medium storing instructions, which, when executed by the machine, cause the machine to perform operations comprising: accessing an integrated circuit design stored in memory, the integrated circuit design comprising a clock tree comprising routes that interconnect a plurality of clock-tree instances; selecting, from the plurality of clock-tree instances of the clock tree, a first clock-tree instance to evaluate for resizing, the first clock-tree instance initially being of a first size; determining a baseline power consumption measurement corresponding to a sub-tree of the first clock-tree instance with the first size of the first clock-tree instance, the determining of the baseline power consumption measurement comprising determining a sum of a first internal power consumption, a first switching power dissipation, and a first leakage power dissipation corresponding to the sub-tree of the first clock-tree instance with the first size of the first clock-tree instance; determining an alternative power consumption measurement corresponding to the sub-tree of the first clock-tree instance with a second size of the first clock-tree instance, the determining of the alternative power consumption measurement comprising determining a sum of a second internal power consumption, a second switching power dissipation, and a second leakage power dissipation corresponding to the sub-tree of the first clock-tree instance with the second size of the first clock tree instance; based on determining that the alternative power consumption measurement is less than the baseline power consumption measurement, upsizing the first clock-tree instance in the clock tree from the first size to the second size; selecting a second clock-tree instance in the clock tree to evaluate for resizing based on a position of the second clock-tree instance in the clock tree relative to a position of the first clock tree instance in the clock tree: downsizing the second clock-tree instance in the clock tree in response to determining that downsizing the second clock-tree instance results in a reduction of power consumption in a sub-tree of the second clock-tree instance; and generating a layout instance for the integrated circuit design based on the upsized first clock-tree instance and the downsized second clock-tree instance, the layout instance describing physical layout dimensions of the integrated circuit design.
2. The system of claim 1 , wherein the operations further comprise: determining a plurality of alternative power consumption measurements corresponding to the sub-tree of the first clock-tree instance, each alternative power consumption measurement corresponding to one of a plurality of alternative sizes of the first clock-tree instance, the plurality of alternative power consumption measurements including the alternative power consumption measurement, the plurality of alternative sizes including the second size; determining that the alternative power consumption measurement is the lowest power consumption measurement of the plurality of power consumption measurements; and based on determining that the alternative power consumption measurement is the lowest power consumption measurement of the plurality of power consumption measurements, selecting the alternative power consumption measurement for comparison with the baseline power consumption measurement.
This invention relates to optimizing power consumption in integrated circuit (IC) clock-tree designs. The problem addressed is efficiently selecting the most power-efficient clock-tree configuration during the design process. Clock trees distribute clock signals across an IC, and their size and structure significantly impact overall power consumption. The invention improves upon prior methods by evaluating multiple alternative clock-tree configurations to identify the most power-efficient option. The system analyzes a sub-tree of a clock-tree instance, calculating power consumption for various alternative sizes of that sub-tree. For each alternative size, a corresponding power consumption measurement is determined. These measurements are compared to identify the alternative with the lowest power consumption. The lowest-power alternative is then selected for further comparison against a baseline power consumption measurement. This ensures that the most power-efficient configuration is chosen during the design process, reducing overall IC power consumption. The method involves evaluating multiple configurations to avoid suboptimal power consumption due to fixed or arbitrary clock-tree sizing decisions. The invention is particularly useful in IC design where minimizing power consumption is critical, such as in mobile or low-power applications.
3. The system of claim 1 , wherein the determining of the alternative power consumption measurement comprises: determining the internal power consumption of the sub-tree of the first clock-tree instance with the second size of the first clock-tree instance; determining the switching power dissipation of the sub-tree of the first clock-tree instance with the second size of the first clock-tree instance; and determining the leakage power dissipation of the sub-tree of the first clock-tree instance with the second size of the first clock-tree instance.
The system relates to power consumption analysis in integrated circuit design, specifically for optimizing clock-tree structures. Clock trees distribute clock signals across a chip, and their design impacts overall power efficiency. The system addresses the challenge of accurately estimating power consumption for different clock-tree configurations to identify optimal designs. The system determines alternative power consumption measurements for a sub-tree of a clock-tree instance. This involves calculating three key components: internal power consumption, switching power dissipation, and leakage power dissipation. Internal power consumption refers to the power used by the sub-tree's internal components, such as buffers and interconnects. Switching power dissipation is the dynamic power consumed during signal transitions, while leakage power dissipation is the static power lost due to leakage currents in the sub-tree. The system evaluates these power metrics for a sub-tree of a first clock-tree instance when scaled to a second size. This allows designers to assess how power consumption changes with different clock-tree configurations, enabling more efficient power management in integrated circuits. By analyzing these power components, the system helps optimize clock-tree designs for reduced energy consumption and improved performance.
4. The system of claim 1 , wherein: the determining of the internal power consumption of the sub-tree of the first clock-tree instance is based on a total power consumed by each cell in the sub-tree; the determining of the switching power dissipation of the sub-tree of the first clock-tree instance is based on a total wirelength of the sub-tree and a load size driven by the sub-tree; and the determining of the leakage power dissipation of the sub-tree of the first clock-tree instance is based on a supply voltage, a switching threshold voltage, and size of the first clock tree instance.
This invention relates to power analysis in clock-tree structures within integrated circuits. The system evaluates power consumption in a clock-tree instance by analyzing sub-trees within the structure. It calculates internal power consumption for a sub-tree by summing the power consumed by each cell in that sub-tree. Switching power dissipation is determined based on the total wirelength of the sub-tree and the load size it drives. Leakage power dissipation is calculated using the supply voltage, switching threshold voltage, and the size of the clock-tree instance. The system compares these power metrics between different clock-tree instances to optimize power efficiency. The approach ensures accurate power estimation by considering both dynamic and static power components, addressing the challenge of balancing performance and energy efficiency in modern integrated circuits. The method supports detailed analysis of clock-tree structures, enabling designers to identify power hotspots and refine the design for lower overall power consumption.
5. The system of claim 1 , wherein the selecting of the first clock-tree instance is based on user input.
A system for clock-tree synthesis in integrated circuit design optimizes clock signal distribution by selecting a first clock-tree instance from multiple candidate instances. The selection is based on user input, allowing designers to choose a specific clock-tree configuration that meets performance, power, or area constraints. The system generates clock-tree instances using a hierarchical approach, where each instance represents a different distribution network for clock signals across the circuit. The selection process considers factors such as signal integrity, timing closure, and power consumption, ensuring the chosen clock-tree meets design requirements. The system may also include a verification module to validate the selected clock-tree against design specifications, ensuring reliability and correctness. By incorporating user input, the system provides flexibility in clock-tree optimization, enabling designers to balance trade-offs between performance and resource usage. This approach improves efficiency in the design process by reducing manual iterations and ensuring optimal clock distribution for high-performance integrated circuits.
6. The system of claim 1 , wherein; the first clock tree instance is a root node of the clock tree, the second clock-tree instance is a downstream clock-tree instance of the root node, and the second clock-tree instance is selected to evaluate for resizing based on the second clock-tree instance being a downstream clock-tree instance of the root node.
The system relates to clock tree synthesis in integrated circuit design, specifically addressing the challenge of optimizing clock tree structures to meet timing and power constraints. Clock trees distribute clock signals across a chip, and their design impacts performance, power consumption, and signal integrity. The system focuses on selecting and resizing specific clock tree instances to improve timing closure and reduce power. The system includes a clock tree with multiple instances, where one instance serves as the root node and others are downstream nodes. The root node is the primary source of the clock signal, while downstream instances receive and distribute the signal further. The system evaluates downstream instances for resizing based on their position in the hierarchy, prioritizing those directly connected to the root node. Resizing involves adjusting the size of clock tree elements (e.g., buffers or wires) to balance signal delay, skew, and power consumption. By targeting downstream instances of the root node, the system ensures that critical path delays are minimized while maintaining signal integrity. This approach helps achieve tighter timing margins and reduces the need for excessive buffering, which can increase power usage. The selection and resizing process is automated, improving efficiency in the design flow. The system is particularly useful in high-performance and low-power integrated circuit designs where clock tree optimization is critical.
7. A method comprising: accessing an integrated circuit design stored in memory, the integrated circuit design comprising a clock tree comprising routes that interconnect a plurality of clock-tree instances; determining, by at least one hardware processor, a baseline power consumption measurement corresponding to a sub-tree of a first clock-tree instance from among the plurality of interconnected clock tree instances, the baseline power consumption measurement corresponding to a first size of the first clock tree instance, the determining of the baseline power consumption measurement comprising determining a sum of a first internal power consumption, a first switching power dissipation, and a first leakage power dissipation corresponding to the sub-tree of the first clock-tree instance with the first size of the first clock-tree instance; determining, by the at least one hardware processor, an alternative power consumption measurement corresponding to the sub-tree with the first clock-tree instance at a second size, the determining of the alternative power consumption measurement comprising determining a sum of a second internal power consumption, a second switching power dissipation, and a second leakage power dissipation corresponding to the sub-tree of the first clock-tree instance with the second size of the first clock tree instance; comparing the alternative power consumption measurement to the baseline power consumption measurement; based on determining the alternative power consumption measurement is less than the baseline power consumption measurement, upsizing, by the at least one hardware processor, the first clock-tree instance in the clock tree according to the second size; selecting a second clock-tree instance in the clock tree to evaluate for resizing based on a position of the second clock-tree instance in the clock tree relative to a position of the first clock tree instance in the clock tree: downsizing the second clock-tree instance in the clock tree in response to determining that downsizing the second clock-tree instance results in a reduction of power consumption in a sub-tree of the second clock-tree instance; and generating a layout instance for the integrated circuit design based on the upsized first clock-tree instance and the downsized second clock-tree instance, the layout instance describing physical layout dimensions of the integrated circuit design.
The method optimizes power consumption in integrated circuit (IC) designs by dynamically resizing clock-tree instances within a clock tree structure. Clock trees distribute clock signals across ICs, but their power efficiency depends on the size and configuration of individual clock-tree instances. The method accesses an IC design with a clock tree comprising interconnected instances and evaluates power consumption for a sub-tree of a first clock-tree instance at its original size, calculating a baseline measurement that sums internal power, switching power dissipation, and leakage power. It then determines an alternative power measurement for the same sub-tree if the first instance were resized, comparing the two to identify power savings. If resizing reduces power, the first instance is upsized accordingly. The method then selects a second clock-tree instance based on its position relative to the first instance and evaluates whether downsizing it reduces power in its sub-tree. If so, the second instance is downsized. The process generates a final IC layout incorporating these adjustments, optimizing overall power efficiency by balancing upsizing and downsizing of clock-tree instances. This approach ensures efficient clock signal distribution while minimizing power consumption.
8. The method of claim 7 , further comprising: determining a plurality of alternative power consumption measurements corresponding to the sub-tree of the first clock tree instance, each alternative power consumption measurement corresponding to one of a plurality of alternative sizes of the first clock-tree instance, the plurality of alternative power consumption measurements including the alternative power consumption measurement, the plurality of alternative sizes including the second size; determining that the alternative power consumption measurement is the lowest power consumption measurement of the plurality of power consumption measurements; and based on determining that the alternative power consumption measurement is the lowest power consumption measurement of the plurality of power consumption measurements, selecting the alternative power consumption measurement for comparison with the baseline power consumption measurement.
This invention relates to optimizing power consumption in integrated circuit (IC) clock tree synthesis. Clock trees distribute clock signals across an IC, and their design significantly impacts power efficiency. The problem addressed is selecting an optimal clock tree configuration that minimizes power consumption while meeting performance constraints. The method involves analyzing a clock tree instance, which is a specific configuration of the clock tree structure. For a sub-tree within this instance, multiple alternative power consumption measurements are calculated, each corresponding to different possible sizes (e.g., buffer sizes or tree depths) of the sub-tree. These measurements include a baseline power consumption value and at least one alternative value. The method then compares these measurements to identify the lowest power consumption value among them. If an alternative configuration yields lower power consumption than the baseline, that alternative is selected for further evaluation against a predefined baseline power consumption measurement. This ensures that the most power-efficient configuration is chosen during the clock tree synthesis process, reducing overall IC power consumption without compromising functionality. The approach helps designers balance power efficiency and performance in IC design.
9. The method of claim 7 , wherein the determining of the alternative power consumption measurement comprises: determining the internal power consumption of the sub-tree of the first clock-tree instance with the second size of the first clock-tree instance; determining the switching power dissipation of the sub-tree of the first clock-tree instance with the second size of the first clock-tree instance; and determining the leakage power dissipation of the sub-tree of the first clock-tree instance with the second size of the first clock-tree instance.
This invention relates to power consumption analysis in integrated circuit design, specifically for optimizing clock-tree structures. The problem addressed is accurately estimating power consumption in clock-tree sub-trees of varying sizes to improve energy efficiency in digital circuits. The method involves analyzing a clock-tree instance by evaluating different configurations to determine optimal power characteristics. The process begins by selecting a sub-tree within a clock-tree instance and analyzing its power consumption at a first size. This includes calculating internal power consumption, switching power dissipation, and leakage power dissipation for the sub-tree. The method then adjusts the size of the clock-tree instance and repeats the power consumption analysis for the sub-tree at this second size. By comparing the power measurements between the two configurations, the invention enables designers to identify the most energy-efficient clock-tree structure. The approach ensures accurate power estimation by considering all relevant power components, including dynamic and static power dissipation, across different clock-tree configurations. This helps in optimizing circuit performance while minimizing power usage.
10. The method of claim 7 , wherein: the determining of the internal power consumption of the sub-tree of the first clock-tree instance is based on a total power consumed by each cell in the sub-tree; the determining of the switching power dissipation of the sub-tree of the first clock-tree instance is based on a total wirelength of the sub-tree and a load size driven by the sub-tree; and the determining of the leakage power dissipation of the sub-tree of the first clock-tree instance is based on a supply voltage, a switching threshold voltage, and size of the first clock tree instance.
This invention relates to power analysis in clock-tree structures within integrated circuits, specifically addressing the challenge of accurately estimating power consumption in clock distribution networks. The method involves analyzing a sub-tree of a clock-tree instance to determine its internal power consumption, switching power dissipation, and leakage power dissipation. Internal power consumption is calculated based on the total power consumed by each cell within the sub-tree. Switching power dissipation is determined using the total wirelength of the sub-tree and the load size it drives, accounting for dynamic power losses in the interconnects. Leakage power dissipation is derived from the supply voltage, switching threshold voltage, and the size of the clock-tree instance, reflecting static power losses. The method enables precise power estimation for optimizing clock-tree designs, reducing overall power consumption, and improving energy efficiency in integrated circuits. By considering both dynamic and static power components, the approach provides a comprehensive assessment of power dissipation in clock networks, aiding in the design of low-power electronic systems.
11. The method of claim 7 , wherein the identifying of the first clock-tree instance is based on user input.
A method for optimizing clock-tree synthesis in integrated circuit design involves identifying a first clock-tree instance based on user input. The clock-tree instance represents a network of clock signals distributed across the circuit to synchronize operations. User input specifies parameters such as timing constraints, power requirements, or design preferences, which guide the selection of the clock-tree instance. The method further includes analyzing the identified clock-tree instance to detect timing violations, such as setup or hold violations, where signal delays cause incorrect circuit behavior. If violations are detected, the method adjusts the clock-tree instance by modifying signal paths, buffer placements, or clock skew to resolve the issues. The adjustments are validated to ensure compliance with design specifications. This approach allows designers to customize clock-tree optimization based on specific project needs, improving timing performance and power efficiency in integrated circuits. The method integrates user-defined criteria with automated analysis and correction to enhance clock distribution accuracy and reliability.
12. The method of claim 7 , wherein; the first clock tree instance is a root node of the clock tree, the second clock-tree instance is a downstream clock-tree instance of the root node, and the second clock-tree instance is selected to evaluate for resizing based on the second clock-tree instance being a downstream clock-tree instance of the root node.
This invention relates to clock tree synthesis in integrated circuit design, specifically optimizing clock tree structures to improve timing performance and reduce power consumption. Clock trees distribute clock signals across a chip, but traditional methods often result in suboptimal timing margins or excessive power usage due to inefficient buffering and routing. The invention addresses this by selectively resizing downstream clock tree instances to balance timing and power efficiency. The method involves analyzing a clock tree structure where a root node (first clock tree instance) distributes signals to downstream nodes (second clock tree instances). The downstream nodes are evaluated for resizing based on their position in the hierarchy, with priority given to nodes directly connected to the root. Resizing adjusts buffer sizes or routing paths to meet timing constraints while minimizing power overhead. This selective approach ensures critical timing paths are optimized without unnecessarily resizing all nodes, reducing overall power consumption. The technique improves upon prior art by dynamically selecting nodes for resizing rather than applying uniform adjustments, leading to more efficient clock distribution. It is particularly useful in high-performance or low-power designs where precise timing and energy efficiency are critical. The method integrates with existing clock tree synthesis tools, enhancing their performance without requiring fundamental architectural changes.
13. A computer storage medium storing instructions, which when executed by a machine, cause the machine to perform operations comprising: accessing an integrated circuit design stored in memory, the integrated circuit design comprising a clock tree comprising routes that interconnect a plurality of clock-tree instances; selecting, from among the plurality of clock-tree instances of the clock tree, a first clock-tree instance to evaluate for resizing, the first clock-tree instance initially being of a first size; determining a baseline power consumption measurement corresponding to a sub-tree of the first clock-tree instance, with the first clock-tree instance at the first size, the determining of the baseline power consumption measurement comprising determining a sum of a first internal power consumption, a first switching power dissipation, and a first leakage power dissipation corresponding to the sub-tree of the first clock-tree instance with the first size of the first clock-tree instance; determining a plurality of alternative power consumption measurements corresponding to the sub-tree of the first clock-tree instance, each alternative power consumption measurement corresponding to one of a plurality of alternative sizes of the first clock-tree instance, the determining of the plurality of alternative power consumption measurements comprising determining an alternative power consumption measurement corresponding to the sub-tree with the first clock-tree instance at a second size, the determining of the alternative power consumption measurement comprising determining a sum of a second internal power consumption, a second switching power dissipation, and a second leakage power dissipation corresponding to the sub-tree of the first clock-tree instance with the second size of the first clock tree instance; determining a lowest alternative power consumption measurement of the plurality of alternative power consumption measurements, the lowest alternative power consumption measurement corresponding to the second size of the first clock-tree instance; comparing the lowest alternative power consumption measurement with the baseline power consumption measurement; based on determining that the lowest alternative power consumption measurement is less than the baseline power consumption measurement, upsizing the first clock-tree instance in the clock tree from the first size to the second size; selecting the second clock-tree instance in the clock tree to evaluate for resizing based on a position of the second clock-tree instance in the clock tree relative to a position of the first clock tree instance in the clock tree: downsizing a second clock-tree instance in the clock tree in response to determining that downsizing the second clock-tree instance results in a reduction of power consumption in a sub-tree of the second clock-tree instance; and generating a layout instance for the integrated circuit design based on the upsized first clock-tree instance and the downsized second clock-tree instance, the layout instance describing physical layout dimensions of the integrated circuit design.
The invention relates to optimizing power consumption in integrated circuit (IC) designs by dynamically resizing clock-tree instances within a clock tree. Clock trees distribute clock signals across an IC, and their design impacts power efficiency. The invention addresses the problem of excessive power consumption in clock trees by evaluating and resizing individual clock-tree instances to minimize power dissipation. The method involves accessing an IC design with a clock tree comprising interconnected clock-tree instances. A first clock-tree instance is selected for evaluation, and its baseline power consumption is measured, including internal power, switching power, and leakage power. Alternative power consumption measurements are calculated for different sizes of the first clock-tree instance. If a smaller size reduces power consumption, the instance is downsized; if a larger size reduces power consumption, it is upsized. The process considers the relative positions of clock-tree instances in the clock tree. After resizing, a layout instance is generated, reflecting the physical dimensions of the optimized IC design. This approach ensures efficient power management by dynamically adjusting clock-tree sizes based on power consumption analysis.
14. The computer storage medium of claim 13 , wherein the determining of the alternative power consumption measurement comprises: determining the internal power consumption of the sub-tree of the first clock-tree instance with the second size of the first clock-tree instance; determining the switching power dissipation of the sub-tree of the first clock-tree instance with the second size of the first clock-tree instance; and determining the leakage power dissipation of the sub-tree of the first clock-tree instance with the second size of the first clock-tree instance.
This invention relates to power consumption analysis in integrated circuit design, specifically for optimizing clock-tree structures. The problem addressed is accurately estimating power dissipation in clock-tree sub-trees to improve energy efficiency in digital circuits. The invention provides a method to determine alternative power consumption measurements for a sub-tree of a clock-tree instance by analyzing three key components: internal power consumption, switching power dissipation, and leakage power dissipation. The process involves evaluating these power metrics for a sub-tree of a first clock-tree instance when it is scaled to a second size. Internal power consumption refers to the power used by the sub-tree's internal components, switching power dissipation measures the dynamic power from signal transitions, and leakage power dissipation accounts for static power losses. By calculating these values for different sizes of the clock-tree instance, designers can optimize the clock-tree structure to minimize overall power consumption while maintaining performance. This approach enables more precise power modeling during the design phase, leading to more energy-efficient integrated circuits. The invention is particularly useful in applications where power efficiency is critical, such as mobile devices, embedded systems, and low-power computing.
15. The computer storage medium of claim 13 , wherein: the determining of the internal power consumption of the sub-tree of the first clock-tree instance is based on a total power consumed by each cell in the sub-tree; the determining of the switching power dissipation of the sub-tree of the first clock-tree instance is based on a total wirelength of the sub-tree and a load size driven by the sub-tree; and the determining of the leakage power dissipation of the sub-tree of the first clock-tree instance is based on a supply voltage, a switching threshold voltage, and size of the first clock tree instance.
This invention relates to power analysis in integrated circuit design, specifically for optimizing clock-tree structures. The problem addressed is the need for accurate power estimation during the design phase to ensure efficient power management in digital circuits. The invention provides a method for analyzing power consumption in a clock-tree instance, focusing on sub-trees within the clock-tree structure. The method involves determining internal power consumption, switching power dissipation, and leakage power dissipation for a sub-tree of a clock-tree instance. Internal power consumption is calculated based on the total power consumed by each cell within the sub-tree. Switching power dissipation is determined using the total wirelength of the sub-tree and the load size driven by the sub-tree. Leakage power dissipation is calculated based on the supply voltage, switching threshold voltage, and size of the clock-tree instance. The invention also includes a technique for generating a second clock-tree instance by modifying the first clock-tree instance and comparing the power consumption of the two instances. This allows designers to evaluate different clock-tree configurations and select the most power-efficient design. The method ensures that power analysis is performed at the sub-tree level, providing granular insights into power distribution within the clock-tree structure. This approach helps in identifying power hotspots and optimizing the clock-tree design for reduced overall power consumption.
16. The computer storage medium of claim 13 , wherein the selecting of the first clock-tree instance is based on user input.
A system and method for optimizing clock-tree synthesis in integrated circuit design involves selecting a clock-tree instance from a plurality of candidate instances to minimize power consumption and signal delay. The selection process evaluates multiple clock-tree instances generated for a given circuit design, comparing their performance metrics such as power efficiency, timing constraints, and signal integrity. The system identifies an optimal clock-tree instance that meets design specifications while minimizing resource usage. User input can be used to influence the selection, allowing designers to prioritize specific performance criteria or constraints. The method ensures that the chosen clock-tree instance balances power efficiency and timing performance, improving overall circuit reliability and energy efficiency. This approach is particularly useful in high-performance and low-power integrated circuit designs where precise clock distribution is critical.
17. The computer storage medium of claim 13 , wherein: the first clock tree instance is a root node of the clock tree, the second clock-tree instance is a downstream clock-tree instance of the root node, and the second clock-tree instance is selected to evaluate for resizing based on the second clock-tree instance being a downstream clock-tree instance of the root node.
This invention relates to optimizing clock tree structures in integrated circuits, specifically addressing the challenge of efficiently resizing clock tree instances to improve timing performance and reduce power consumption. Clock trees distribute clock signals across a chip, and their design impacts signal integrity, power efficiency, and timing margins. The invention focuses on selecting and resizing downstream clock tree instances to enhance performance. The method involves identifying a root node of the clock tree and evaluating downstream instances connected to it. A second clock tree instance, positioned downstream from the root, is selected for resizing based on its hierarchical relationship. Resizing adjustments are made to this downstream instance to optimize timing and power characteristics. The process may include analyzing timing constraints, power consumption, and signal propagation delays to determine the optimal resizing parameters. By targeting downstream instances, the method ensures that critical timing paths are prioritized while minimizing unnecessary modifications to the overall clock tree structure. This approach improves clock signal distribution efficiency without disrupting the broader clock network. The invention is implemented using computer storage media, enabling automated analysis and optimization of clock tree designs in integrated circuit layouts.
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October 6, 2020
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