Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A signal transmitting and receiving apparatus, comprising: a first on-die termination circuit connected to a first pin through which a first signal is transmitted or received and, when enabled, the first on-die termination circuit is configured to provide a first termination resistance to a signal line connected to the first pin; a second on-die termination circuit connected to a second pin through which a second signal is transmitted or received and, when enabled, the second on-die termination circuit is configured to provide a second termination resistance to a signal line connected to the second pin; and an on-die termination control circuit configured to independently control an enable time and a disable time of each of the first on-die termination circuit and the second on-die termination circuit, wherein the signal transmitting and receiving apparatus receives the first signal from outside the signal transmitting and receiving apparatus through the first pin before the second on-die termination circuit is enabled after the first on-die termination circuit is enabled, and the first signal is a data signal and the second signal is a read data strobe signal.
This invention relates to signal transmitting and receiving apparatuses, particularly those used in high-speed data communication systems where precise timing and signal integrity are critical. The apparatus includes two on-die termination (ODT) circuits connected to separate pins, each providing termination resistance to their respective signal lines when enabled. The first ODT circuit is connected to a pin transmitting or receiving a data signal, while the second ODT circuit is connected to a pin handling a read data strobe signal. An ODT control circuit independently manages the enable and disable timing of each ODT circuit. The apparatus ensures that the data signal is received before the second ODT circuit is activated after the first ODT circuit is enabled, optimizing signal integrity and timing synchronization in data transmission. This design addresses challenges in high-speed interfaces where mismatched termination timing can lead to signal reflections, data errors, or performance degradation. The independent control of ODT circuits allows for fine-tuned termination adjustments, improving reliability in data communication systems.
2. The signal transmitting and receiving apparatus of claim 1 , wherein, when in a first mode in which the first pin does not require the first termination resistance and the second pin does not require the second termination resistance, the on-die termination control circuit is configured to disable the first on-die termination circuit and the second on-die termination circuit.
This invention relates to signal transmitting and receiving apparatuses, specifically those with on-die termination (ODT) circuits for impedance matching in high-speed data communication. The problem addressed is the unnecessary power consumption and signal integrity issues caused by active termination circuits when they are not needed, such as during low-speed or idle modes. The apparatus includes a first pin and a second pin for transmitting and receiving signals, along with a first on-die termination circuit and a second on-die termination circuit connected to these pins. Each termination circuit is designed to provide a specific termination resistance (first and second termination resistance, respectively) to match the impedance of the transmission line and prevent signal reflections. An on-die termination control circuit dynamically manages these termination circuits based on the operating mode of the apparatus. In a first mode, where neither the first nor the second pin requires termination resistance (e.g., during low-speed or idle states), the control circuit disables both termination circuits to conserve power and avoid unnecessary loading. This selective disabling ensures that termination is only active when needed, improving energy efficiency and signal quality. The apparatus may also include additional features, such as a termination resistance adjustment circuit to fine-tune the termination values for optimal performance. The invention is particularly useful in high-speed interfaces like DDR memory, where dynamic termination control is critical for reducing power consumption and maintaining signal integrity.
3. The signal transmitting and receiving apparatus of claim 2 , wherein, when a second mode in which the first pin requires the first termination resistance and the second pin requires the second termination resistance switches to the first mode, the on-die termination control circuit is configured to disable the first on-die termination circuit a predetermined time after the second on-die termination circuit is disabled.
This invention relates to signal transmitting and receiving apparatuses, specifically those with configurable termination resistances for different operating modes. The problem addressed is ensuring proper signal integrity during mode switching in high-speed communication systems where termination resistances must be dynamically adjusted. The apparatus includes multiple pins, each requiring different termination resistances in different modes. For example, in a first mode, a first pin may require a first termination resistance, while a second pin may require a second termination resistance. In a second mode, the termination requirements may change, necessitating adjustments to maintain signal integrity. The apparatus includes on-die termination circuits for each pin, controlled by an on-die termination control circuit. When switching from the second mode to the first mode, the control circuit disables the second on-die termination circuit before disabling the first on-die termination circuit, with a predetermined delay between the two actions. This staggered disabling ensures that termination resistances are adjusted in a controlled manner, preventing signal reflections or other integrity issues during mode transitions. The predetermined time delay is set to allow stable signal conditions before the next termination adjustment. This approach is particularly useful in high-speed interfaces where rapid mode switching is common, such as in memory controllers or high-speed serial links.
4. The signal transmitting and receiving apparatus of claim 1 , wherein, when a first mode in which the first pin does not require the first termination resistance and the second pin does not require the second termination resistance switches to a second mode in which the first pin requires the first termination resistance and the second pin requires the second termination resistance, the on-die termination control circuit is configured to enable the second on-die termination circuit a predetermined time after the first on-die termination circuit is enabled.
This invention relates to signal transmitting and receiving apparatuses, particularly those with on-die termination (ODT) circuits for managing signal integrity in high-speed communication systems. The problem addressed is the need to properly sequence the activation of termination resistances when switching between operational modes that require different termination configurations. The apparatus includes a first pin and a second pin, each with associated termination resistances (first and second termination resistances, respectively). An on-die termination control circuit manages the activation of these resistances through first and second on-die termination circuits. In a first mode, neither pin requires termination resistance, while in a second mode, both pins require termination. When transitioning from the first mode to the second mode, the control circuit enables the first termination circuit and then, after a predetermined delay, enables the second termination circuit. This staggered activation prevents signal integrity issues that could arise from simultaneous termination changes, ensuring stable signal transmission during mode switching. The predetermined delay is set to avoid reflections or noise that could disrupt communication. This approach is particularly useful in systems where termination requirements vary dynamically, such as in memory interfaces or high-speed serial links.
5. The signal transmitting and receiving apparatus of claim 1 , wherein a time period, during which the first on-die termination circuit is disabled, is included in a time period, during which the second on-die termination circuit is disabled.
This invention relates to signal transmitting and receiving apparatuses, specifically those incorporating multiple on-die termination (ODT) circuits to manage signal integrity in high-speed data communication. The problem addressed is the need to optimize termination control to reduce power consumption and improve signal quality during data transmission and reception. The apparatus includes at least two on-die termination circuits, each configured to adjust impedance to match transmission line characteristics. The first termination circuit is associated with a transmitter, while the second is linked to a receiver. To enhance efficiency, the apparatus ensures that the time period during which the first termination circuit is disabled is entirely contained within the time period when the second termination circuit is also disabled. This overlapping disablement reduces power consumption by preventing unnecessary activation of termination circuits when they are not required for signal integrity. The coordinated disablement also minimizes signal reflections and distortions, particularly during transitions between active and idle states. The apparatus may further include control logic to dynamically adjust termination settings based on operational conditions, ensuring optimal performance across varying data rates and environmental factors. This approach is particularly useful in high-speed interfaces such as memory controllers, processors, and communication chips where power efficiency and signal integrity are critical.
6. The signal transmitting and receiving apparatus of claim 5 , wherein the signal transmitting and receiving apparatus transmits the first signal through the first pin in the time period, during which the first on-die termination circuit is disabled, and transmits the second signal through the second pin in the time period, during which the second on-die termination circuit is disabled.
This invention relates to signal transmitting and receiving apparatuses, particularly those used in high-speed data communication systems where signal integrity is critical. The apparatus addresses the problem of signal reflection and distortion caused by on-die termination (ODT) circuits, which are used to match impedance and reduce signal reflections but can interfere with signal transmission when active. The apparatus includes a first pin and a second pin for transmitting and receiving signals, along with a first on-die termination circuit connected to the first pin and a second on-die termination circuit connected to the second pin. The ODT circuits are selectively enabled or disabled to control signal transmission. The apparatus transmits a first signal through the first pin during a time period when the first ODT circuit is disabled, ensuring the signal is not degraded by termination resistance. Similarly, it transmits a second signal through the second pin during a time period when the second ODT circuit is disabled. This staggered activation ensures that signals are transmitted only when the corresponding ODT circuit is inactive, minimizing reflections and improving signal quality. The apparatus may also include a control circuit to manage the timing of ODT activation and signal transmission, ensuring proper synchronization. This approach enhances data transmission efficiency and reliability in high-speed communication systems.
7. The signal transmitting and receiving apparatus of claim 6 , wherein the signal transmitting and receiving apparatus transmits the second signal through the second pin in the time period, during which the first on-die termination circuit is disabled.
This invention relates to signal transmitting and receiving apparatuses used in high-speed data communication systems, particularly those employing on-die termination (ODT) circuits to manage signal integrity. The problem addressed is the interference that occurs when multiple signals are transmitted or received simultaneously through shared or adjacent pins, leading to signal degradation and communication errors. The invention provides a solution by coordinating the timing of signal transmission and ODT circuit activation to minimize interference. The apparatus includes a first pin for transmitting or receiving a first signal and a second pin for transmitting or receiving a second signal. An on-die termination circuit is connected to the first pin to control impedance matching during signal transmission or reception. The apparatus is configured to transmit the second signal through the second pin during a specific time period when the first on-die termination circuit is disabled. This ensures that the second signal is not affected by the impedance changes caused by the first ODT circuit, reducing crosstalk and improving signal integrity. The apparatus may also include additional termination circuits and pins for further signal management, with similar timing coordination to prevent interference. The invention is particularly useful in high-speed interfaces where multiple signals must be transmitted or received simultaneously without degradation.
8. A method of operating an apparatus that transmits or receives a first signal through a first pin and a second signal through a second pin, the method comprising: disabling a first on-die termination circuit and a second on-die termination circuit, the first on-die termination circuit being connected to the first pin, and the second on-die termination circuit being connected to the second pin; enabling the first on-die termination circuit such that the first on-die termination circuit provides a first termination resistance to a signal line connected to the first pin; enabling the second on-die termination circuit such that the second on-die termination circuit provides a second termination resistance to a signal line connected to the second pin, wherein the second on-die termination circuit is enabled a period of time after the first on-die termination circuit is enabled; and receiving the first signal from outside the apparatus through the first pin before the second on-die termination circuit is enabled after the first on-die termination circuit is enabled, wherein the first signal is a data signal and the second signal is a read data strobe signal.
This invention relates to signal transmission and reception in electronic devices, specifically addressing termination control for high-speed data interfaces. The problem solved involves managing signal integrity and timing in systems where data and strobe signals are transmitted or received through separate pins, such as in memory interfaces. On-die termination (ODT) circuits are used to reduce signal reflections, but improper timing can degrade performance. The method operates an apparatus with two pins: one for a data signal and another for a read data strobe signal. Initially, both on-die termination circuits connected to these pins are disabled. The termination circuit for the data signal pin is enabled first, providing a termination resistance to the signal line. After a delay, the termination circuit for the strobe signal pin is enabled. During this delay, the apparatus receives the data signal from an external source before the strobe signal's termination is activated. This staggered activation ensures proper signal alignment and reduces interference, improving data integrity in high-speed communication. The technique is particularly useful in memory systems where precise timing between data and strobe signals is critical.
9. The method of claim 8 , wherein the disabling of the first on-die termination circuit and the second on-die termination circuit comprises: disabling the second on-die termination circuit; and disabling the first on-die termination circuit after a first time period elapses from when the second on-die termination circuit is disabled.
This invention relates to memory systems, specifically to methods for managing on-die termination (ODT) circuits in memory devices to improve signal integrity and power efficiency. The problem addressed is the need to optimize termination control during memory operations, particularly when transitioning between different termination states to minimize signal reflections and power consumption. The method involves selectively disabling two on-die termination circuits in a staggered manner. First, a second on-die termination circuit is disabled. Then, after a predetermined time delay, a first on-die termination circuit is disabled. This staggered disabling process helps prevent signal integrity issues that could arise from simultaneous termination changes, ensuring stable data transmission. The time delay between disabling the two circuits allows for proper signal settling, reducing the risk of reflections or noise that could corrupt data. The method is particularly useful in high-speed memory systems where precise termination control is critical for reliable operation. By sequentially disabling the termination circuits, the system maintains signal integrity while efficiently managing power consumption. This approach is applicable in various memory technologies, including DRAM, where termination control plays a key role in performance and energy efficiency.
10. The method of claim 8 , further comprising: transmitting a first signal through the first pin before the first on-die termination circuit is enabled after the first on-die termination circuit is disabled; and transmitting a second signal through the second pin before the second on-die termination circuit is enabled after the second on-die termination circuit is disabled.
This invention relates to signal transmission in electronic systems, specifically addressing challenges in managing on-die termination (ODT) circuits during signal transmission. ODT circuits are used to match impedance in high-speed interfaces, reducing signal reflections and improving signal integrity. However, enabling or disabling these circuits can introduce transient noise or signal disturbances, particularly when multiple ODT circuits are involved in a system. The invention describes a method for transmitting signals through multiple pins in a system where each pin is associated with an ODT circuit. Before enabling an ODT circuit after it has been disabled, a signal is transmitted through the corresponding pin. This ensures that the signal path is stable and minimizes disruptions caused by ODT activation. The method applies to at least two pins, each with its own ODT circuit, where a first signal is transmitted through a first pin before enabling its ODT circuit, and a second signal is transmitted through a second pin before enabling its ODT circuit. This approach helps maintain signal integrity during transitions in ODT states, particularly in systems where multiple ODT circuits are dynamically controlled. The technique is useful in high-speed communication interfaces, memory systems, and other applications where precise signal timing and low noise are critical.
11. The method of claim 10 , wherein the transmitting of the second signal comprises transmitting the second signal through the second pin before the first on-die termination circuit is enabled after the first on-die termination circuit is disabled.
A method for managing signal transmission in an integrated circuit involves controlling on-die termination (ODT) circuits to optimize signal integrity during data transfer. The method addresses the challenge of maintaining signal quality in high-speed communication interfaces, particularly when switching between different transmission modes or states. The technique ensures that termination circuits are properly disabled and enabled to prevent signal reflections and distortions that can degrade performance. The method includes transmitting a first signal through a first pin while a first on-die termination circuit is enabled. When a transition to a different state or mode occurs, the first ODT circuit is disabled to prevent interference. A second signal is then transmitted through a second pin before the first ODT circuit is re-enabled. This sequential control ensures that the termination circuit does not interfere with the second signal, maintaining signal integrity during the transition. The approach is particularly useful in memory interfaces, such as DDR (Double Data Rate) systems, where precise timing and termination control are critical for reliable data transfer. By coordinating the timing of ODT circuit activation and deactivation with signal transmission, the method minimizes signal degradation and improves overall system performance.
12. A memory device, comprising: a first on-die termination circuit connected to a data pin for transmitting or receiving a data signal and, when enabled, the first on-die termination circuit is configured to provide a first termination resistance to a signal line connected to the data pin; a second on-die termination circuit connected to a read data strobe pin for transmitting or receiving a read data strobe signal and, when enabled, the second on-die termination circuit is configured to provide a second termination resistance to a signal line connected to the read data strobe pin; and an on-die termination control circuit configured to independently control an enable timing or a disable timing of the first on-die termination circuit and an enable timing or a disable timing of the second on-die termination circuit, wherein the memory device receives the data signal from outside the memory device through the data pin before the second on-die termination circuit is enabled after the first on-die termination circuit is enabled.
This invention relates to memory devices with improved on-die termination (ODT) control for data and read data strobe (DQS) signals. The problem addressed is signal integrity and timing mismatches in high-speed memory interfaces, where improper termination can cause reflections, noise, and data errors. The memory device includes two on-die termination circuits: one connected to a data pin (DQ) and another to a read data strobe pin (DQS). Each termination circuit provides a configurable resistance to its respective signal line when enabled. A control circuit independently manages the enable/disable timing of both termination circuits. The data pin's termination is activated first, allowing the memory device to receive incoming data signals before the DQS termination is enabled. This staggered activation ensures proper signal alignment and reduces interference between data and strobe signals during read operations. The independent control allows for optimized termination timing based on specific memory interface requirements, improving signal integrity and reliability in high-speed memory systems.
13. The memory device of claim 12 , wherein the on-die termination control circuit is configured to disable the second on-die termination circuit after a first time period elapses since the memory device received a data read command and disable the first on-die termination circuit after a second time period elapses since the memory device received the data read command, the second time period being greater than the first time period.
This invention relates to memory devices with on-die termination (ODT) control for optimizing signal integrity during data read operations. The problem addressed is the need to dynamically adjust termination resistance to reduce power consumption and signal reflections while maintaining data integrity during read operations. The memory device includes multiple on-die termination circuits, including a first termination circuit for a data bus and a second termination circuit for a command/address bus. An on-die termination control circuit manages these circuits by disabling them at different times after receiving a read command. The second termination circuit (for the command/address bus) is disabled after a first time period, while the first termination circuit (for the data bus) remains active for a longer second time period. This staggered disablement ensures that command/address signals are terminated only as long as necessary, reducing power consumption, while data bus termination is maintained longer to support sustained data transfer. The control circuit may use timing logic or a counter to measure the elapsed time since the read command was received, ensuring precise termination control. This approach improves energy efficiency without compromising signal quality during read operations.
14. The memory device of claim 13 , wherein the on-die termination control circuit is configured to enable the first on-die termination circuit after a third time period elapses since the memory device received the data read command and enable the second on-die termination circuit after a fourth time period elapses since the memory device received the data read command, the fourth time period being greater than the third time period.
This invention relates to memory devices with on-die termination (ODT) control for optimizing data read operations. The problem addressed is the need to dynamically adjust termination impedance to reduce signal reflections and improve signal integrity during read operations, particularly in high-speed memory systems. The memory device includes a first on-die termination (ODT) circuit and a second ODT circuit, each connected to a data bus. An on-die termination control circuit manages the activation of these circuits. The first ODT circuit is enabled after a first time period following the receipt of a data read command, while the second ODT circuit is enabled after a second time period, which is longer than the first. This staggered activation ensures proper termination timing, reducing signal distortion and improving data integrity during read operations. The control circuit may also disable the first ODT circuit after a third time period and the second ODT circuit after a fourth time period, where the fourth time period is longer than the third. This sequential activation and deactivation of the ODT circuits optimizes termination for different phases of the read operation, enhancing signal quality and system performance. The invention is particularly useful in high-speed memory systems where precise termination control is critical for reliable data transmission.
15. The memory device of claim 12 , wherein the memory device transmits the data signal outside the memory device through the data pin and transmits the read data strobe signal outside the memory device through the read data strobe pin, before the first on-die termination circuit is enabled after the first on-die termination circuit is disabled.
This invention relates to memory devices, specifically addressing signal transmission and termination control to improve data integrity during read operations. The memory device includes a data pin for transmitting data signals and a read data strobe pin for transmitting read data strobe signals. The device also features an on-die termination (ODT) circuit that can be enabled or disabled to control signal reflection and impedance matching. The invention ensures that data and strobe signals are transmitted outside the memory device through their respective pins before the ODT circuit is re-enabled after being disabled. This prevents signal integrity issues that could arise from enabling the ODT circuit too early, such as signal distortion or timing errors. The ODT circuit is typically disabled during read operations to allow the memory device to drive signals without interference, and re-enabled afterward to maintain proper termination for subsequent operations. The invention ensures that the data and strobe signals are fully transmitted before the ODT circuit is reactivated, minimizing the risk of signal degradation. This approach enhances reliability in high-speed memory systems where precise timing and signal quality are critical.
16. The memory device of claim 12 , further comprising a data clock signal pin for receiving a data clock signal from outside the memory device, wherein the read data strobe pin is configured to output, as the read data strobe signal, a signal synchronized with the data clock signal in a read operation of the memory device.
This invention relates to memory devices, specifically addressing synchronization challenges in read operations. The memory device includes a read data strobe pin that outputs a read data strobe signal synchronized with an external data clock signal during read operations. The device also features a data clock signal pin for receiving the external data clock signal, ensuring precise timing alignment between the read data strobe signal and the data clock signal. This synchronization improves data integrity and reliability by reducing timing mismatches during read operations. The memory device may also include a write data strobe pin for receiving a write data strobe signal during write operations, further enhancing data transfer accuracy. The invention aims to optimize memory performance by ensuring that the read data strobe signal accurately tracks the external data clock signal, minimizing errors in data retrieval. This solution is particularly useful in high-speed memory systems where precise timing is critical for reliable data communication.
17. The memory device of claim 12 , wherein the memory device provides an indicator signal outside the memory device through a mode register, the indicator signal indicating that the memory device has the ability to independently control the first on-die termination circuit and the second on-die termination circuit.
This invention relates to memory devices with enhanced on-die termination (ODT) control capabilities. The problem addressed is the lack of independent control over multiple ODT circuits within a single memory device, which can lead to suboptimal signal integrity and performance in high-speed memory systems. The invention provides a memory device with at least two on-die termination circuits, where each circuit can be independently controlled. The memory device includes a mode register that generates an indicator signal accessible outside the device, signaling its ability to independently control the first and second ODT circuits. This allows external systems, such as memory controllers, to dynamically adjust termination settings for different memory channels or ranks without requiring additional external components. The independent control of ODT circuits improves signal integrity, reduces power consumption, and enhances overall system performance by optimizing termination resistance based on specific operational conditions. The mode register-based indicator signal ensures compatibility with existing systems while enabling advanced termination management features.
Unknown
October 6, 2020
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