Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A method of determining dimensional changes attributed to variation of location in a simulation field, comprising: receiving data describing a unit cell comprising a plurality of features; calculating a spacing to be used between adjacent unit cells so that the features of the unit cell will sample a simulation field; correcting the unit cell for proximity effects caused by replicas of the unit cell, the replicas of the unit cell forming a border around the unit cell and positioned relative to the unit cell at the calculated spacing; generating an array of unit cells, each unit cell in the array of unit cells being a replica of the unit cell corrected for proximity effects, and positioned relative to neighboring unit cells in the array of unit cells at the calculated spacing; dividing the array of unit cells into a plurality of templates, each template framing a respective portion of the array of unit cells, wherein locations of a first portion of the unit cells framed by a first template of the plurality of templates are shifted relative to locations of a second portion of the unit cells framed by a second template of the plurality of templates; determining, for each of the plurality of templates, a plurality of critical dimensions each representing a size of a feature of the plurality of features at a location within the simulation field; obtaining shift variances of the plurality of features based at least in part on the critical dimensions; and determining a dimensional change of a feature of the plurality of features based on a corresponding shift variance of the features.
This invention relates to a method for analyzing dimensional changes in a simulation field due to variations in feature placement. The method addresses the challenge of accurately modeling proximity effects in lithography or other simulation fields where feature dimensions can vary based on their location relative to neighboring features. The process begins by receiving data describing a unit cell containing multiple features. A spacing between adjacent unit cells is calculated to ensure the features sample the simulation field effectively. The unit cell is then corrected for proximity effects caused by neighboring replicas of the unit cell, which are positioned at the calculated spacing to form a border around the original unit cell. An array of these corrected unit cells is generated, with each unit cell spaced according to the calculated spacing. The array is divided into multiple templates, each framing a portion of the array. The locations of unit cells in one template are shifted relative to those in another template. For each template, critical dimensions of the features are determined at various locations within the simulation field. Shift variances of the features are derived from these critical dimensions, and the dimensional change of a feature is determined based on its corresponding shift variance. This method enables precise analysis of how feature placement affects dimensional variations in a simulation field.
2. The method of claim 1 , wherein the locations of the first portion of the unit cells framed by the first template are shifted in both a horizontal direction and a vertical direction relative to the locations of the second portion of the unit cells framed by the second template.
This invention relates to a method for arranging unit cells in a display panel, addressing the challenge of improving display uniformity and reducing visual artifacts such as moiré patterns. The method involves using two distinct templates to frame different portions of unit cells, where the locations of the first portion of unit cells framed by the first template are intentionally shifted in both horizontal and vertical directions relative to the second portion of unit cells framed by the second template. This staggered arrangement disrupts regular patterns that can cause interference effects, enhancing display quality. The first template defines the positions of a subset of unit cells, while the second template defines the positions of another subset, with the shift ensuring that the overall pixel layout avoids repetitive structures that lead to visual distortions. The method is particularly useful in high-resolution displays where pixel density is high, and alignment errors or periodic patterns can degrade performance. By introducing controlled positional shifts between the two portions of unit cells, the invention mitigates artifacts while maintaining precise control over pixel placement.
3. The method of claim 1 , wherein determining, for each template, the plurality of critical dimensions comprises simulating each of the plurality of templates independently from the others of the plurality of templates.
The invention relates to a method for determining critical dimensions in semiconductor manufacturing, specifically for optimizing template designs used in lithography processes. The problem addressed is the need to accurately and efficiently identify critical dimensions for multiple templates without excessive computational overhead, ensuring precise pattern fidelity during semiconductor fabrication. The method involves simulating each template independently to determine its critical dimensions. This independent simulation allows for precise analysis of each template's behavior without interference from other templates, improving accuracy in identifying critical dimensions. The critical dimensions are key measurements that define the smallest and most precise features of the template, which are essential for ensuring the correct patterning of semiconductor devices. By simulating each template separately, the method avoids the computational complexity and potential inaccuracies that can arise from simulating multiple templates simultaneously. This approach ensures that the critical dimensions are determined with high fidelity, leading to improved lithography performance and reduced defects in the final semiconductor devices. The method is particularly useful in advanced semiconductor manufacturing where precision and efficiency are critical.
4. The method of claim 1 , wherein the shift variances of the plurality of features are obtained by simulating implementations of the plurality of features on the simulation field for each of the plurality of templates.
This invention relates to a method for analyzing shift variances in semiconductor manufacturing, specifically for optimizing feature placement on a simulation field. The problem addressed is the variability in feature positioning during manufacturing, which can lead to defects or performance issues in integrated circuits. The method involves simulating the implementation of multiple features on a simulation field for each of a plurality of templates. By doing so, the shift variances of these features can be determined, allowing for adjustments to minimize misalignment and improve manufacturing yield. The simulation process accounts for variations in process conditions, such as lithography, etching, or deposition, to predict how features will behave under real-world manufacturing constraints. The resulting shift variance data can then be used to refine feature designs or adjust manufacturing parameters, ensuring better consistency and reliability in the final product. This approach helps manufacturers identify potential issues early in the design phase, reducing costly rework and improving overall production efficiency.
5. The method of claim 1 , wherein calculating a spacing to be used between adjacent unit cells comprises calculating a first spacing for a horizontal spacing and a second spacing for a vertical spacing.
This invention relates to the design and optimization of unit cell spacing in a structured layout, such as those used in semiconductor manufacturing or photonic crystal design. The problem addressed is the need to precisely control the spacing between adjacent unit cells to achieve desired performance characteristics, such as optical properties, thermal management, or electrical conductivity, while avoiding interference or unintended interactions between adjacent cells. The method involves calculating separate horizontal and vertical spacings between unit cells to optimize their arrangement. The horizontal spacing is determined based on factors such as the unit cell's width, the desired pitch, and any constraints related to manufacturing tolerances or functional requirements. Similarly, the vertical spacing is calculated independently, taking into account the unit cell's height, alignment needs, and performance criteria. By treating horizontal and vertical spacings as distinct parameters, the method allows for finer control over the unit cell layout, enabling better optimization of the overall structure. This approach ensures that the spacing between unit cells is tailored to specific design goals, whether for minimizing cross-talk, maximizing efficiency, or improving manufacturability. The method may be applied in various fields, including integrated circuit design, photonic devices, and metamaterials, where precise control over unit cell spacing is critical.
6. The method of claim 1 , wherein each template of the plurality of templates has a length in a direction different from any integer multiple of a sum of (i) a length of the unit cell in the direction, and (ii) the calculated spacing.
This invention relates to a method for designing templates used in a process involving periodic structures, such as lithography or materials science. The problem addressed is ensuring precise alignment and interaction between templates and a unit cell structure, where misalignment can lead to defects or inefficiencies. The method involves generating a plurality of templates, each with a specific length in a given direction. This length is intentionally chosen to avoid being an integer multiple of the sum of two components: (1) the length of the unit cell in that direction, and (2) a calculated spacing value. By avoiding such integer multiples, the method prevents undesirable periodic overlaps or interference patterns that could disrupt the intended functionality of the templates. The calculated spacing may be derived from physical constraints, such as material properties or process tolerances, ensuring compatibility with the unit cell structure. The templates are designed to interact with the unit cell in a controlled manner, optimizing performance in applications like nanolithography, where precise patterning is critical. The method ensures that the templates do not align in a way that reinforces or cancels out desired features, maintaining accuracy and reliability in the final product.
7. The method of claim 1 , wherein the calculated spacing is less than an ambit distance, two features separated by at least the ambit distance not causing a proximity effect.
This invention relates to semiconductor manufacturing, specifically to methods for determining feature spacing to avoid proximity effects during lithography. Proximity effects occur when closely spaced features on a mask interact during exposure, leading to distortions in the printed pattern. The invention addresses the challenge of optimizing feature spacing to prevent these effects while maintaining design density. The method calculates a spacing between features on a semiconductor mask. The calculated spacing is set to be less than an ambit distance, which is defined as the minimum separation at which features no longer influence each other during lithographic exposure. Features spaced at or beyond this ambit distance do not cause proximity effects, ensuring accurate pattern transfer. The method ensures that features are spaced closely enough to maximize chip density while avoiding unwanted interactions. The invention may involve comparing feature positions to determine if they fall within the ambit distance and adjusting spacing accordingly. It may also include iterative calculations to refine spacing values based on lithography process parameters. The method can be applied to various semiconductor manufacturing processes, including photolithography and extreme ultraviolet (EUV) lithography, where proximity effects are particularly problematic. By dynamically adjusting spacing, the invention improves yield and reduces the need for costly design iterations.
8. The method of claim 1 , further comprising generating a plurality of markers for uniquely identifying each of the plurality of features within the unit cell.
A method for analyzing a unit cell structure in materials science or crystallography involves generating a plurality of markers to uniquely identify each of the plurality of features within the unit cell. The unit cell is a repeating structural unit that defines the arrangement of atoms, molecules, or other features in a crystalline material. The method addresses the challenge of accurately distinguishing and tracking individual features within the unit cell, which is critical for understanding material properties, phase transitions, and defect analysis. By assigning unique markers to each feature, the method enables precise identification and differentiation of features, facilitating detailed structural characterization. The markers may include numerical, alphanumeric, or symbolic identifiers that are distinct for each feature, ensuring no ambiguity in feature recognition. This approach enhances the accuracy of subsequent analyses, such as defect mapping, strain analysis, or computational modeling, by providing a clear and unambiguous reference for each feature. The method is particularly useful in fields like materials science, nanotechnology, and crystallography, where precise structural information is essential for advancing research and development.
9. The method of claim 1 , further comprising: identifying one of the plurality of features having a shift variance exceeding a predetermined threshold; and in response to identifying the feature, correcting a model for performing optical proximity correction.
The invention relates to semiconductor manufacturing, specifically to improving optical proximity correction (OPC) in lithography processes. The problem addressed is the presence of feature shifts in photomask patterns that exceed acceptable tolerances, leading to inaccuracies in the final semiconductor device. These shifts can occur due to variations in the lithography process, causing misalignment or distortion in the printed features. The method involves analyzing a plurality of features in a photomask design to detect those with shift variances that exceed a predetermined threshold. When such a feature is identified, the system automatically corrects the OPC model used to generate the photomask. This correction ensures that the lithography process compensates for the identified shifts, improving the accuracy of the printed features on the wafer. The OPC model adjustment may involve modifying bias, sizing, or other parameters to mitigate the detected shift variance. By dynamically correcting the OPC model in response to shift detection, the method enhances the reliability of the lithography process, reducing defects and improving yield in semiconductor manufacturing. The approach is particularly useful in advanced node fabrication where feature sizes are extremely small, and even minor shifts can significantly impact device performance.
10. The method of claim 1 , further comprising: comparing a subset of the critical dimensions associated with a feature, each critical dimension of the feature measured at a different replicas of the unit cell, wherein a shift variance of the feature is obtained based on the comparison of the subset of the critical dimensions associated with the feature.
The invention relates to semiconductor manufacturing, specifically to methods for analyzing critical dimensions (CDs) of features in a unit cell to assess variability across multiple replicas. In semiconductor fabrication, ensuring uniformity of features like transistors or interconnects is crucial for device performance. However, variations in critical dimensions across replicas of the same unit cell can lead to inconsistencies in electrical properties and yield loss. The invention addresses this by measuring critical dimensions of a feature at different replicas of the unit cell and comparing these dimensions to determine a shift variance. This variance quantifies the degree of positional or dimensional inconsistency in the feature across replicas, enabling process optimization and defect detection. The method involves selecting a subset of critical dimensions associated with the feature, measuring these dimensions at multiple replicas, and analyzing the measurements to derive the shift variance. This approach helps identify and mitigate systematic or random variations in the manufacturing process, improving yield and reliability. The technique is particularly useful in advanced node semiconductor manufacturing where feature sizes are extremely small and variability has a significant impact on performance.
11. The method of claim 1 , wherein the spacing is calculated so that the features of the unit cell will sample the simulation field with the exception of a one ambit border for context of the remainder of the simulation field, and the calculated spacing is less than one ambit.
This invention relates to computational simulations, specifically methods for optimizing the sampling of a simulation field within a unit cell structure. The problem addressed is the efficient and accurate representation of a simulation field while minimizing computational resources. The method involves calculating the spacing of features within a unit cell such that the features sample the simulation field, except for a one ambit border area, which provides contextual information about the surrounding field. The calculated spacing is intentionally set to be less than one ambit to ensure sufficient sampling density. The unit cell structure is designed to repeat across the simulation field, allowing the method to balance accuracy and computational efficiency. The one ambit border serves as a buffer zone, ensuring that the sampled features within the unit cell are not isolated but are influenced by the broader simulation context. This approach reduces the need for excessive sampling while maintaining the integrity of the simulation results. The method is particularly useful in fields such as material science, electromagnetics, and fluid dynamics, where accurate field representation is critical but computational resources are limited. By optimizing the spacing of features within the unit cell, the invention enables more efficient simulations without sacrificing accuracy.
12. A method of determining dimensional changes attributed to variation of location in a simulation field of a unit cell having a plurality of features, the unit cell corrected, using an optical proximity correction (OPC) model, for proximity effects caused by replicas of the unit cell, the replicas of the unit cell forming a border around the unit cell and positioned relative to the unit cell at a calculated spacing, the method comprising: dividing an array of unit cells comprising a plurality of unit cells positioned relative to each other at the calculated spacing into a plurality of templates, each template framing a respective portion of the array of unit cells, wherein locations of a first portion of the plurality of unit cells framed by a first template of the plurality of templates are shifted relative to locations of a second portion of the plurality of unit cells framed by a second template of the plurality of templates; determining, for each of the plurality of templates, using a simulation algorithm, a plurality of critical dimensions each representing a size of a feature of the plurality of features at a location within the simulation field; obtaining shift variances of the plurality of features based at least in part on the critical dimensions; determining that the shift variances are above a selected threshold; and in response to determining that the shift variances are above the selected threshold, repeating the method with an adjustment to at least one of the OPC model and the simulation algorithm until the shift variance is below the selected threshold.
This method addresses the challenge of accurately simulating and correcting dimensional variations in a unit cell structure due to proximity effects in lithography. The unit cell, which contains multiple features, is surrounded by replicas positioned at a calculated spacing to simulate the influence of neighboring cells. The method involves dividing an array of these unit cells into multiple templates, where each template frames a portion of the array. The locations of unit cells within one template may be shifted relative to those in another template. For each template, a simulation algorithm calculates critical dimensions (sizes of features) at various locations within the simulation field. Shift variances of the features are then derived from these critical dimensions. If the shift variances exceed a predefined threshold, the method iterates by adjusting either the optical proximity correction (OPC) model or the simulation algorithm until the shift variance falls below the threshold. This ensures that the unit cell's dimensions are accurately corrected for proximity effects, improving lithography precision.
13. The method of claim 12 , further comprising: in response to determining that the shift variances are below the selected threshold, determining that the OPC model can be used in a design process.
This invention relates to optical proximity correction (OPC) modeling in semiconductor manufacturing, specifically addressing the challenge of validating OPC models to ensure accurate lithography results. The method involves analyzing shift variances in model predictions compared to actual lithography outcomes. If these variances fall below a predefined threshold, the OPC model is deemed suitable for use in the design process. The method includes generating a test pattern, simulating its lithography outcome using the OPC model, and measuring the shift variances between the simulated and actual results. Additional steps involve adjusting the test pattern or model parameters to refine accuracy. The invention ensures that OPC models meet performance criteria before deployment, reducing lithography errors and improving semiconductor yield. The approach is particularly useful in advanced node manufacturing where precision is critical. By validating the model's predictive accuracy, the method prevents costly fabrication errors and enhances design reliability. The system may integrate with existing OPC tools to streamline model validation workflows.
14. The method of claim 11 , wherein determining that the shift variances are above a selected threshold comprises comparing each shift variance to the selected threshold and determining that at least one shift variance is above the selected threshold.
This invention relates to a method for analyzing shift variances in a system, particularly in applications where precise positional or timing adjustments are critical, such as in manufacturing, robotics, or sensor calibration. The problem addressed is the need to accurately detect when positional or timing shifts exceed acceptable limits, ensuring system performance remains within specified tolerances. The method involves monitoring shift variances, which are deviations from a reference position or timing. These variances are compared against a predefined threshold to determine if they exceed acceptable limits. If at least one shift variance surpasses the threshold, the system identifies this as an out-of-tolerance condition, triggering corrective actions such as adjustments, alerts, or shutdowns. The threshold can be dynamically adjusted based on system requirements or environmental conditions. The method may also include preprocessing the shift data, such as filtering noise or normalizing values, to improve accuracy. Additionally, it may involve logging the results for further analysis or compliance reporting. The approach ensures that minor fluctuations do not trigger unnecessary responses while reliably detecting significant deviations that could impact system integrity or output quality. This is particularly useful in automated systems where real-time monitoring and adaptive responses are essential.
15. The method of claim 11 , wherein determining that the shift variances are above a selected threshold comprises at least one of: comparing a minimum shift variance to a selected minimum shift variance threshold, and determining that the minimum shift variance is above the selected minimum shift variance threshold; and comparing a mean shift variance to a selected mean shift variance threshold, and determining that the mean shift variance is above the selected mean shift variance threshold.
This invention relates to a method for analyzing shift variances in a system, particularly in applications where precise positional or temporal alignment is critical, such as manufacturing, robotics, or signal processing. The problem addressed is the need to accurately detect when shift variances exceed acceptable limits, ensuring system performance and reliability. The method involves evaluating shift variances to determine if they surpass predefined thresholds. Specifically, it compares a minimum shift variance to a selected minimum shift variance threshold and checks if the minimum shift variance exceeds this threshold. Additionally, it compares a mean shift variance to a selected mean shift variance threshold and verifies if the mean shift variance exceeds this threshold. If either condition is met, the method concludes that the shift variances are above the acceptable limit. This approach allows for robust monitoring of system alignment or synchronization, enabling timely corrective actions when deviations become significant. The thresholds can be adjusted based on system requirements, ensuring flexibility in different operational contexts. The method is particularly useful in applications where maintaining tight tolerances is essential, such as automated assembly lines, robotic control systems, or time-sensitive data processing. By detecting excessive shift variances early, the method helps prevent errors, improve efficiency, and maintain system integrity.
16. The method of claim 11 , wherein the locations of the first portion of the unit cells framed by the first template are shifted in both a horizontal direction and a vertical direction relative to the locations of the second portion of the unit cells framed by the second template.
This invention relates to a method for arranging unit cells in a display panel, particularly for improving display uniformity and reducing visual artifacts. The method involves using two templates to frame different portions of unit cells, where the locations of the first portion of unit cells framed by the first template are shifted in both horizontal and vertical directions relative to the second portion of unit cells framed by the second template. This shifting helps to distribute pixel misalignments and reduce moiré patterns, enhancing display quality. The templates define the spatial arrangement of unit cells, ensuring precise positioning while allowing controlled offsets between the two portions. The method may be applied in manufacturing processes for display panels, such as OLED or LCD screens, to optimize pixel alignment and minimize visual distortions. The shifting of unit cell locations in both directions ensures that any alignment errors are evenly distributed, improving overall display performance. The technique is particularly useful in high-resolution displays where pixel density is high, and alignment precision is critical. The method may also include additional steps for verifying alignment accuracy and adjusting the templates to achieve the desired shifting effect. The invention addresses the problem of pixel misalignment in display manufacturing, which can lead to visible artifacts and reduced image quality. By systematically shifting unit cell positions, the method provides a solution that enhances display uniformity and visual clarity.
17. The method of claim 11 , wherein determining, for each template, the plurality of critical dimensions comprises simulating each of the plurality of templates independently from the others of the plurality of templates.
The invention relates to a method for determining critical dimensions in semiconductor manufacturing, specifically for optimizing template designs used in lithography processes. The problem addressed is the need to accurately and efficiently identify critical dimensions for multiple templates, which are essential for ensuring precise pattern transfer during semiconductor fabrication. Traditional methods may involve time-consuming or computationally intensive processes that do not account for the unique characteristics of each template. The method involves simulating each template independently to determine its critical dimensions. This independent simulation allows for precise analysis of each template's behavior under lithographic conditions without interference from other templates. The critical dimensions, which are key measurements affecting the template's performance, are derived from these simulations. By simulating each template separately, the method ensures that the critical dimensions are accurately identified for each template, leading to improved lithography accuracy and yield. This approach is particularly useful in advanced semiconductor manufacturing where high precision is required. The method can be integrated into design and manufacturing workflows to enhance template optimization and reduce errors in pattern transfer.
18. The method of claim 11 , wherein the shift variances of the plurality of features are obtained by simulating implementations of the plurality of features on the simulation field for each of the plurality of templates using the simulation algorithm.
This invention relates to a method for analyzing shift variances in integrated circuit (IC) design, particularly for optimizing feature placement to improve manufacturing yield. The problem addressed is the variability in feature placement during IC fabrication, which can lead to defects and reduced yield. The method involves simulating the behavior of multiple features on a simulation field for each of a plurality of templates using a simulation algorithm. By simulating implementations of these features, the method calculates the shift variances that occur during the manufacturing process. These shift variances represent deviations in feature placement from their intended positions, which can impact circuit performance and reliability. The simulation algorithm models the physical and chemical processes involved in IC fabrication, such as lithography, etching, and deposition, to predict how features will shift under different conditions. The method then uses these shift variances to optimize the design, ensuring that features are placed in a way that minimizes variability and improves yield. This approach allows designers to identify potential issues early in the design phase, reducing the need for costly rework and improving overall manufacturing efficiency. The simulation-based analysis provides a more accurate prediction of feature behavior compared to traditional methods, leading to more robust and reliable IC designs.
19. The method of claim 11 , wherein each template of the plurality of templates has a length in a direction different from any integer multiple of a sum of (i) a length of the unit cell in the direction, and (ii) the calculated spacing.
This invention relates to a method for designing templates used in nanolithography or similar patterning processes. The method addresses the challenge of optimizing template dimensions to avoid interference patterns that degrade precision in nanoscale fabrication. The core technique involves generating a plurality of templates, each with a specific length in a given direction. This length is intentionally set to be non-integer relative to the sum of two key parameters: (1) the length of the unit cell in that direction and (2) a calculated spacing value derived from the fabrication process. By ensuring the template length avoids integer multiples of this sum, the method prevents constructive or destructive interference effects that could distort the final patterned structure. The approach is particularly useful in fields like semiconductor manufacturing, where precise control over nanoscale features is critical. The method may be applied iteratively to refine template designs, ensuring compatibility with existing fabrication constraints while minimizing unwanted interactions. The calculated spacing accounts for process-specific variables such as beam divergence or material properties, allowing for adaptability across different nanolithography techniques. The result is a set of optimized templates that enhance patterning accuracy and reproducibility.
20. The method of claim 11 , wherein the calculated spacing is less than an ambit distance, two features separated by at least the ambit distance not causing a proximity effect.
This invention relates to semiconductor manufacturing, specifically to methods for determining feature spacing to avoid proximity effects during lithography. Proximity effects occur when closely spaced features on a mask interact during exposure, leading to distortions in the printed pattern. The invention addresses the challenge of optimizing feature spacing to prevent these effects while maintaining design density. The method calculates a spacing between features on a semiconductor mask. The calculated spacing is set to be less than an ambit distance, which is defined as the minimum separation distance at which two features no longer influence each other during lithographic exposure. Features spaced at or beyond this ambit distance do not cause proximity effects, ensuring accurate pattern transfer. The method may involve analyzing feature dimensions, exposure conditions, and lithography system characteristics to determine the appropriate ambit distance. By enforcing spacing constraints below this threshold, the method ensures consistent feature printing without proximity-induced distortions. This approach is particularly useful in advanced semiconductor nodes where feature sizes are extremely small, and proximity effects are more pronounced. The method can be integrated into design rule checks or optical proximity correction (OPC) processes to improve yield and reliability in semiconductor manufacturing.
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October 20, 2020
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