Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A memory channel interleaving method for a power reduction or a performance improvement, the method comprising: remapping a memory access address for a first memory device and/or a second memory device, each of the first memory device and the second memory device including an interleaving access region and a linear access region, the memory access address including an interleaving access area for a performance improvement use and a linear access area for a power reduction use; receiving, at a linear address remapping logic, a selection signal to select an interleaving mode for performance improvement or a linear mode for power reduction; deciding, by the linear address remapping logic, whether the memory access address corresponds to the interleaving access area or the linear access area; performing an interleaving access operation on the interleaving access regions in the first and second memory devices in the interleaving mode; and performing a linear access operation on the linear access region in only one of the first and second memory devices in the linear mode, wherein the first memory device is associated with a first port and a memory controller, and the second memory device is associated with a second port and the memory controller.
This invention relates to memory systems and addresses the problem of optimizing memory access for either power reduction or performance improvement. The method involves remapping memory access addresses for multiple memory devices, specifically a first and a second memory device. Each memory device has two distinct access regions: an interleaving access region and a linear access region. The memory access address itself is also divided into two areas: an interleaving access area intended for performance enhancement and a linear access area for power reduction. A selection signal is received by linear address remapping logic, indicating whether to operate in an interleaving mode for performance or a linear mode for power saving. Based on this signal, the remapping logic determines if the memory access address falls within the interleaving or linear access area. In the interleaving mode, an interleaving access operation is performed across the interleaving access regions of both the first and second memory devices. This mode is designed for performance improvement. In the linear mode, a linear access operation is performed on the linear access region of only one of the memory devices. This mode is designed for power reduction. The first memory device is connected via a first port to a memory controller, and the second memory device is connected via a second port to the same memory controller.
2. The method of claim 1 , further comprising performing a partial interleaving access operation without requiring a change of the memory controller.
A system and method for memory access optimization in computing devices addresses inefficiencies in data retrieval from memory modules, particularly in scenarios requiring partial interleaving. Traditional memory controllers often lack flexibility, leading to suboptimal performance when accessing non-contiguous data blocks. The invention introduces a technique for performing partial interleaving access operations without modifying the existing memory controller hardware or firmware. This is achieved by dynamically adjusting access patterns at the system level, allowing selective interleaving of data requests while maintaining compatibility with standard memory architectures. The method involves analyzing memory access patterns, identifying segments of data that benefit from interleaving, and routing requests accordingly without disrupting the controller's standard operation. This approach improves data throughput and reduces latency for specific workloads, such as those involving irregular data access patterns or mixed criticality tasks. The solution is particularly useful in systems where hardware modifications are impractical, providing a software-driven or firmware-driven enhancement to memory performance. By leveraging existing memory infrastructure, the invention offers a cost-effective way to optimize partial interleaving without requiring controller redesign.
3. The method of claim 1 , wherein the first port and the second port operate simultaneously in the interleaving mode, and only one of the first port and the second port operates in the linear mode.
This invention relates to a communication system that supports both interleaving and linear modes of operation for data transmission. The system includes at least two ports, each capable of operating in either mode. In interleaving mode, data is transmitted in a time-division manner, allowing multiple ports to share a communication channel efficiently. In linear mode, a single port transmits data continuously without sharing the channel. The invention ensures that when both ports are active, they operate simultaneously in interleaving mode, while only one port can operate in linear mode at a time. This prevents conflicts and optimizes bandwidth usage. The system dynamically switches between modes based on data traffic demands, ensuring efficient resource allocation. The invention is particularly useful in high-speed communication networks where flexible and efficient data transmission is required.
4. The method of claim 1 , wherein each of the first memory device and the second memory device is a dynamic random access memory (DRAM) device.
This invention relates to memory systems, specifically addressing challenges in data storage and retrieval efficiency in computing systems. The invention describes a method for managing data storage between two memory devices to improve performance and reliability. The method involves transferring data between a first memory device and a second memory device based on predefined criteria, such as data access patterns or system workload. The transfer process ensures that frequently accessed data is stored in a more accessible memory device, while less frequently accessed data is moved to a secondary memory device. This dynamic allocation optimizes memory usage and reduces latency in data retrieval. The invention further specifies that both the first and second memory devices are dynamic random access memory (DRAM) devices, which are known for their high-speed data access capabilities. By dynamically managing data placement between these DRAM devices, the system can enhance overall performance, reduce power consumption, and improve data reliability. The method includes monitoring data access patterns, determining optimal data placement, and executing the transfer of data between the memory devices to maintain efficient operation. This approach is particularly useful in systems where memory resources are limited or where performance is critical.
5. The method of claim 1 , wherein the linear address remapping logic is placed between a bus connection unit and the memory controller.
A system and method for improving memory access efficiency in computing systems involves linear address remapping logic positioned between a bus connection unit and a memory controller. The bus connection unit interfaces with a processor or other computing components to receive memory access requests, while the memory controller manages physical memory operations. The linear address remapping logic dynamically translates virtual or logical memory addresses into physical memory addresses, optimizing memory access patterns to reduce latency and improve performance. This remapping logic can handle address translations for various memory access operations, including read, write, and prefetch requests, ensuring efficient use of memory resources. The placement of the remapping logic between the bus connection unit and memory controller allows for seamless integration into existing system architectures while minimizing additional hardware overhead. The system may also include error detection and correction mechanisms to ensure data integrity during address translation. This approach enhances memory system performance by reducing address translation bottlenecks and improving overall system efficiency.
6. A system for providing a memory channel interleaving for a power reduction or a performance improvement, the system comprising: a first memory device, including a first interleaving access region and a first linear access region; a second memory device including a second interleaving access region and a second linear access region; a system on chip (SoC) comprising a linear address remapping logic and a memory controller, wherein the linear address remapping logic is configured to remap a memory access address for the first memory device and/or a second memory device, the memory access address including an interleaving access area for a performance improvement use and a linear access area for a power reduction use, the linear address remapping logic is configured to receive a selection signal to select an interleaving mode for performance improvement or a linear mode for power reduction, the linear address remapping logic is configured to decide whether the memory access address corresponds to the interleaving access area or the linear access area, wherein an interleaving access operation is performed on the interleaving access regions in the first and second memory devices in the interleaving mode, and a linear access operation is performed on the linear access region in only one of the first and second memory devices in the linear mode, the first memory device is associated with a first port, and the second memory device is associated with a second port.
This invention relates to a system for optimizing memory access in electronic devices, addressing the trade-off between power consumption and performance. The system includes two memory devices, each with distinct access regions: an interleaving access region for performance optimization and a linear access region for power reduction. A system-on-chip (SoC) integrates a linear address remapping logic and a memory controller. The remapping logic dynamically remaps memory access addresses based on a selection signal, directing operations to either interleaving or linear access regions. In interleaving mode, data is distributed across both memory devices to enhance performance, while in linear mode, access is confined to a single device to minimize power usage. The SoC's memory controller manages these operations, ensuring efficient data handling. This approach allows devices to switch between high-performance and low-power states as needed, improving energy efficiency without sacrificing performance when required. The system leverages separate ports for each memory device to facilitate seamless transitions between access modes.
7. The system of claim 6 , wherein the first memory device is associated with the memory controller, and the second memory device is associated with the memory controller.
This invention relates to a memory system architecture designed to improve data access efficiency and reliability. The system includes a memory controller connected to at least two memory devices, where each memory device is directly associated with the memory controller. The memory controller manages data storage and retrieval operations across the memory devices, ensuring coordinated access and reducing latency. The system may also include additional components such as a processor or a host interface to facilitate communication between the memory devices and external systems. The memory devices may be of the same or different types, such as DRAM, NAND flash, or other storage technologies, depending on the application. The architecture allows for parallel data access, load balancing, and fault tolerance by distributing data across multiple memory devices. This design is particularly useful in high-performance computing, data centers, and embedded systems where efficient memory management is critical. The system may also include error correction mechanisms to enhance data integrity and reliability. By associating both memory devices with the same memory controller, the system ensures seamless coordination and optimized performance.
8. The system of claim 6 , wherein the memory controller is configured to perform the interleaving access operation or the linear access operation according to the interleaving mode or the linear mode.
A system for managing memory access operations includes a memory controller that selectively performs either interleaved or linear access operations based on a configurable mode. The system addresses the challenge of optimizing memory access patterns to improve performance and efficiency in computing systems. Interleaved access operations distribute memory requests across multiple memory channels or banks to enhance parallelism and reduce latency, while linear access operations sequentially access memory locations within a single channel or bank to minimize overhead. The memory controller dynamically switches between these modes to adapt to different workload requirements, such as balancing latency and throughput or accommodating specific application needs. The system may also include memory modules and a host processor that interact with the memory controller to execute the selected access operations. By providing flexible access strategies, the system ensures efficient memory utilization and performance optimization for various computing tasks.
9. The system of claim 6 , wherein the memory controller performs a partial interleaving access operation without requiring a change of the memory controller.
The system involves a memory controller designed to optimize data access in memory systems, particularly addressing inefficiencies in traditional interleaving techniques. Interleaving is a method used to improve memory performance by distributing data across multiple memory modules or banks to reduce latency and enhance bandwidth. However, conventional interleaving methods often require significant modifications to the memory controller or system architecture, leading to increased complexity and cost. This system introduces a memory controller capable of performing partial interleaving access operations without necessitating changes to the controller's hardware or firmware. Partial interleaving allows selective interleaving of specific data patterns or access sequences, rather than applying full interleaving across all memory operations. This approach reduces overhead while still improving performance for critical workloads. The memory controller dynamically determines when and how to apply partial interleaving based on access patterns, system load, or other performance metrics, ensuring flexibility and efficiency. By avoiding the need for controller modifications, the system simplifies integration into existing memory architectures and reduces development costs. The solution is particularly useful in high-performance computing, data centers, and embedded systems where memory efficiency is critical.
10. The system of claim 6 , wherein the memory controller performs the interleaving access operation to the interleaving access region.
A system for managing memory access operations includes a memory controller configured to perform interleaving access operations to a designated interleaving access region within a memory device. The interleaving access region is a specific portion of the memory that is optimized for interleaved data access, improving performance by distributing access operations across multiple memory banks or channels. The memory controller dynamically allocates and manages this region to ensure efficient data retrieval and storage. The system may also include a memory device with multiple banks or channels, where the interleaving access region spans these components to enable parallel access. The memory controller coordinates these accesses to minimize latency and maximize throughput, particularly for workloads requiring high-speed data transfer. The system may further include error detection and correction mechanisms to maintain data integrity during interleaved operations. This approach enhances memory performance by reducing bottlenecks and improving access efficiency in high-demand applications.
11. The system of claim 6 , wherein the memory controller performs the linear access operation to the linear access region.
A system for managing memory access operations includes a memory controller that performs linear access operations to a designated linear access region within a memory device. The linear access region is a contiguous block of memory addresses that allows for sequential read or write operations without requiring address translation or complex addressing schemes. The memory controller is configured to execute these linear access operations efficiently, reducing latency and improving performance for applications that require continuous data streaming, such as video processing, real-time data analysis, or high-speed data transfers. The system may also include additional features, such as error detection and correction mechanisms, to ensure data integrity during linear access operations. The memory controller may further support dynamic allocation or reconfiguration of the linear access region based on system requirements, allowing flexibility in memory management. This approach optimizes memory bandwidth utilization and minimizes overhead associated with address translation, making it suitable for high-performance computing environments.
12. The system of claim 6 , wherein the first port and the second port operate simultaneously data in the interleaving mode, and only one of the first port and the second port operates in the linear mode.
A system for managing data transmission between multiple ports includes a first port and a second port, each capable of operating in either an interleaving mode or a linear mode. In the interleaving mode, data is transmitted in a time-division multiplexed manner, allowing multiple data streams to share the same port. In the linear mode, a single data stream is transmitted without interleaving. The system is configured such that both ports can operate simultaneously in the interleaving mode, enabling concurrent transmission of multiple data streams. However, only one of the two ports can operate in the linear mode at any given time, ensuring that the other port remains in interleaving mode. This design allows for flexible data handling, optimizing throughput and resource allocation based on the specific requirements of the data streams. The system may be used in communication networks, data processing units, or other applications where efficient data transmission is critical. The invention addresses the need for adaptable port configurations that balance performance and resource utilization.
13. The system of claim 6 , wherein each of the first memory device and the second memory device is a dynamic random access memory (DRAM) device.
This invention relates to a memory system designed to improve data storage and retrieval efficiency in computing environments. The system addresses the challenge of managing data access latency and power consumption in memory devices, particularly in scenarios requiring high-speed data processing. The system includes a first memory device and a second memory device, each configured to store data and communicate with a processing unit. The first memory device is connected to the second memory device via a communication link, enabling data transfer between them. The system further includes a controller that manages data operations, such as reading, writing, and refreshing, across the memory devices. The controller optimizes data placement and access patterns to reduce latency and power consumption. In this embodiment, both the first and second memory devices are dynamic random access memory (DRAM) devices, which are known for their high-speed data access capabilities but require periodic refreshing to retain data integrity. The system leverages the properties of DRAM to enhance performance while mitigating the limitations associated with traditional memory architectures. The communication link between the memory devices allows for parallel data processing and efficient data sharing, improving overall system throughput. The controller dynamically adjusts data distribution and access strategies based on workload demands, ensuring optimal performance under varying conditions. This approach enhances data access efficiency, reduces energy consumption, and improves system reliability in computing applications.
14. The system of claim 6 , wherein the linear address remapping logic is placed between a bus connection unit and the memory controller.
A system for managing memory access in a computing environment addresses the challenge of efficiently remapping linear addresses to physical addresses while minimizing latency and complexity. The system includes a linear address remapping logic unit that translates virtual or linear addresses to physical memory addresses, ensuring proper data access and storage. This remapping logic is strategically positioned between a bus connection unit and a memory controller. The bus connection unit handles data transfers between the processor and other system components, while the memory controller manages interactions with physical memory. By placing the remapping logic in this intermediate position, the system optimizes address translation without disrupting the flow of data between the bus and memory controller. This configuration reduces latency by avoiding redundant address translations and simplifies the overall memory access pipeline. The system is particularly useful in high-performance computing environments where efficient memory management is critical for system performance. The remapping logic may include hardware-based translation mechanisms, such as page tables or translation lookaside buffers (TLBs), to accelerate address resolution. The system ensures compatibility with existing memory architectures while improving address translation efficiency.
15. A system on chip (SoC) comprising: a linear address remapping logic configured to remap a memory access address for a first memory device and/or a second memory device, and configured to receive a selection signal to select an interleaving mode for performance improvement or a linear mode for power reduction; and a memory controller configured to perform a partial interleaving access operation, wherein the memory access address includes an interleaving access area for a performance improvement use and a linear access area for a power reduction use, and the linear address remapping logic is configured to decide whether the memory access address corresponds to the interleaving access area or the linear access area, wherein an interleaving access operation is performed on interleaving access areas in the first and second memory devices in the interleaving mode, and a linear access operation is performed on a linear access area in only one of the first and second memory devices in the linear mode.
This invention relates to a system on chip (SoC) designed to optimize memory access for performance and power efficiency. The system addresses the challenge of balancing performance demands with power consumption in memory-intensive applications. The SoC includes a linear address remapping logic that remaps memory access addresses for two memory devices. This logic receives a selection signal to choose between an interleaving mode for performance improvement or a linear mode for power reduction. The memory controller performs partial interleaving access operations based on the remapped addresses. The memory access address is divided into an interleaving access area for performance optimization and a linear access area for power savings. The linear address remapping logic determines whether the address falls into the interleaving or linear access area. In interleaving mode, access operations are distributed across both memory devices to enhance performance. In linear mode, access is restricted to a single memory device to reduce power consumption. This approach allows dynamic adjustment between performance and power efficiency based on system requirements.
16. The SoC of claim 15 , wherein the memory controller performs the partial interleaving access operation without requiring a change of the memory controller.
A system-on-chip (SoC) integrates a memory controller designed to perform partial interleaving access operations without requiring modifications to the memory controller hardware or firmware. The SoC includes a memory subsystem with multiple memory channels, where the memory controller dynamically selects a subset of these channels for interleaved access based on workload requirements. This partial interleaving optimizes memory bandwidth utilization by distributing data across fewer channels than the full set, reducing power consumption and latency while maintaining performance for specific workloads. The memory controller independently manages the interleaving process, allowing flexible adaptation to different memory access patterns without hardware redesign. This approach is particularly useful in embedded systems and mobile devices where power efficiency and performance tuning are critical. The invention addresses the challenge of balancing memory performance and energy efficiency by enabling dynamic, workload-aware interleaving without altering the underlying memory controller architecture.
17. The SoC of claim 15 , wherein the memory controller performs the interleaving access operation or the linear access operation according to the interleaving mode or the linear mode.
A system-on-chip (SoC) includes a memory controller configured to manage data access to a memory device. The memory controller supports two distinct access modes: an interleaving mode and a linear mode. In the interleaving mode, the memory controller distributes data access operations across multiple memory banks or channels to improve performance and reduce latency by leveraging parallel access capabilities. In the linear mode, the memory controller performs sequential access operations within a single memory bank or channel, which can be more efficient for certain workloads that require contiguous data retrieval or storage. The memory controller dynamically selects between these modes based on system requirements, workload characteristics, or predefined configurations to optimize memory performance. This dual-mode operation enhances flexibility and efficiency in memory access, addressing challenges related to latency, bandwidth utilization, and power consumption in SoC-based systems. The memory controller may also include additional features such as error correction, address translation, or power management to further improve reliability and performance.
18. A memory channel interleaving method for a power reduction or a performance improvement, the method comprising: remapping a memory access address for two or more memory devices accessed via two or more respective memory ports with an interleaving access area and a linear access area, the interleaving access area comprising memory addresses for an interleaving access operation for the performance improvement, the linear access area comprising memory addresses for a linear access operation for the power reduction; receiving a signal that includes a power reduction mode or a performance improvement mode; and performing the interleaving access operation or the linear access operation according to the performance improvement mode or the power reduction mode.
This invention relates to memory channel interleaving techniques for optimizing power consumption and performance in memory systems. The method addresses the challenge of balancing power efficiency and performance in systems with multiple memory devices accessed via separate memory ports. By dynamically remapping memory access addresses, the system can switch between interleaved and linear access modes based on operational requirements. The method involves partitioning memory addresses into two distinct regions: an interleaving access area and a linear access area. The interleaving access area is used for interleaved access operations, which improve performance by distributing memory requests across multiple memory devices. The linear access area is used for linear access operations, which reduce power consumption by minimizing unnecessary memory device activations. The system receives a signal indicating whether to prioritize power reduction or performance improvement, then selects the appropriate access mode accordingly. This dynamic adjustment allows the system to optimize for either low-power operation or high-performance operation as needed. The method ensures efficient memory management by leveraging the strengths of both interleaved and linear access strategies.
19. The method of claim 18 , wherein the linear access area comprises a first address range associated with a first memory device among the two or more memory devices and accessed via a first port among the two or more memory ports, and a second address range associated with a second memory device among the two or more memory devices and accessed via a second port among the two or more memory ports.
This invention relates to memory access optimization in systems with multiple memory devices and ports. The problem addressed is inefficient memory access when multiple devices and ports are involved, leading to bottlenecks and reduced performance. The solution involves organizing memory access into linear and non-linear areas, where linear access areas are specifically mapped to distinct address ranges and memory devices, each accessed via dedicated ports. The linear access area includes a first address range assigned to a first memory device, accessed through a first port, and a second address range assigned to a second memory device, accessed through a second port. This segmentation allows parallel access to different memory devices via their respective ports, improving throughput and reducing contention. The non-linear access area handles remaining memory operations not optimized for linear access. The system dynamically manages these areas to balance performance and resource utilization, ensuring efficient data retrieval and storage across multiple memory devices and ports. This approach is particularly useful in high-performance computing environments where minimizing access latency and maximizing bandwidth are critical.
20. The method of claim 19 , wherein the performing the linear access operation comprises using the first address range associated with the first memory device while the second memory device is placed in the power reduction mode.
This invention relates to memory management in computing systems, specifically optimizing power consumption during linear access operations. The problem addressed is the inefficiency in power usage when accessing memory devices, particularly in systems with multiple memory devices where one device is idle or underutilized while another is active. The method involves performing a linear access operation on a first memory device while a second memory device is placed in a power reduction mode. The first memory device is associated with a first address range, and the second memory device is associated with a second address range. The system dynamically adjusts power states based on access patterns, ensuring that only the necessary memory devices are fully powered while others are in a low-power state. This reduces overall power consumption without degrading performance for active operations. The method includes monitoring memory access patterns to determine when linear access operations are being performed on the first memory device. When such operations are detected, the second memory device is transitioned to a power reduction mode, such as a standby or sleep state, to conserve energy. The system may also restore the second memory device to an active state when access to its address range is required. This approach is particularly useful in systems with multiple memory modules, such as dual-channel or multi-channel memory configurations, where power efficiency is critical. The invention ensures that memory access remains efficient while minimizing unnecessary power draw from idle devices.
21. The method of claim 20 , further comprising when a last memory address in the first address range of the linear access area is reached: placing the first memory device in the power reduction mode; activating the second memory device; and performing the linear access operation in the power reduction mode for the second address range associated with the second memory device.
This invention relates to memory management in computing systems, specifically addressing power efficiency during linear access operations across multiple memory devices. The problem solved is the excessive power consumption when accessing large contiguous memory blocks, particularly in systems with multiple memory devices. The invention provides a method to reduce power consumption by dynamically switching between memory devices during linear access operations. The method involves a system with at least two memory devices, each having an address range assigned to a linear access area. During a linear access operation, the system monitors the memory address being accessed. When the last address in the first memory device's address range is reached, the system places the first memory device into a power reduction mode, such as a low-power or standby state. Simultaneously, the second memory device is activated, and the linear access operation continues seamlessly in the second memory device's address range. This ensures uninterrupted data access while minimizing power consumption by deactivating unused memory devices. The method may also include pre-fetching data from the second memory device before the last address of the first memory device is reached, ensuring no performance degradation during the transition. The power reduction mode may involve reducing clock speeds, voltage levels, or disabling certain memory components. The invention is particularly useful in portable or battery-powered devices where power efficiency is critical.
22. The method of claim 18 , wherein the linear access operation is performed in the linear access area with a first memory device among the two or more memory devices in the performance improvement mode and a second memory device among the two or more memory devices in the power reduction mode.
This invention relates to memory systems designed to optimize performance and power efficiency. The problem addressed is balancing the need for high-speed data access with reduced power consumption in memory systems, particularly in scenarios where different memory devices operate in distinct modes to achieve this balance. The invention involves a memory system with two or more memory devices, where at least one device operates in a performance improvement mode while another operates in a power reduction mode. The system performs linear access operations—such as sequential read or write operations—in a designated linear access area. In this configuration, a first memory device handles the linear access operation in the performance improvement mode, prioritizing speed and responsiveness. Simultaneously, a second memory device operates in the power reduction mode, minimizing energy consumption. This dual-mode approach allows the system to dynamically adjust performance and power usage based on workload demands, ensuring efficient resource allocation without compromising overall system functionality. The invention may also include additional features, such as adaptive mode switching, load balancing, or error handling, to further enhance reliability and efficiency.
23. The method of claim 18 , wherein the interleaving access area or the linear access area comprises a bit specifying a memory device.
A method for managing memory access in a storage system addresses the challenge of efficiently organizing data to optimize read and write operations. The system divides memory into interleaved and linear access areas, each configured to handle different types of data access patterns. The interleaved access area is structured to allow concurrent access to multiple memory devices, improving performance for operations requiring parallel data retrieval or storage. The linear access area is optimized for sequential access, reducing latency for operations that process data in a linear sequence. A key feature of the method involves a bit within either the interleaved or linear access area that specifies a particular memory device, enabling precise control over data routing and access. This bit ensures that data is directed to the correct memory device, enhancing reliability and performance. The method dynamically adjusts access patterns based on workload demands, balancing between interleaved and linear modes to maximize efficiency. By integrating this bit-based device specification, the system achieves finer granularity in memory management, reducing conflicts and improving overall system throughput. The approach is particularly useful in high-performance storage environments where access patterns vary dynamically.
24. The method of claim 18 , wherein a memory controller receives the signal that includes the power reduction mode or the performance improvement mode via a bus connection unit.
A method for managing power and performance in a computing system involves a memory controller that receives a signal indicating either a power reduction mode or a performance improvement mode. The signal is transmitted through a bus connection unit, which facilitates communication between the memory controller and other system components. The memory controller adjusts its operations based on the received signal to either reduce power consumption or enhance performance. In power reduction mode, the memory controller may lower clock speeds, disable unused components, or enter low-power states to minimize energy usage. In performance improvement mode, the controller may increase clock speeds, enable additional memory channels, or prioritize high-speed operations to boost system responsiveness. The bus connection unit ensures reliable signal transmission, allowing the memory controller to dynamically switch between modes based on system demands. This approach optimizes energy efficiency and performance without requiring hardware modifications, making it suitable for various computing applications.
25. The method of claim 18 , further comprising adjusting a bandwidth balance among the two or more memory devices through the interleaving access operation.
This invention relates to memory access optimization in systems with multiple memory devices, addressing inefficiencies in bandwidth utilization and access latency. The method involves interleaving access operations across two or more memory devices to improve performance. By distributing memory requests among the devices, the system can mitigate bottlenecks and reduce latency, particularly in high-demand scenarios. The method includes dynamically adjusting the bandwidth balance among the memory devices during interleaving to optimize resource allocation based on current workload conditions. This adjustment ensures that memory access is evenly distributed or prioritized as needed, enhancing overall system efficiency. The interleaving process may involve coordinating read and write operations across the devices to minimize contention and maximize throughput. The invention is particularly useful in computing systems where multiple memory devices are used to support high-performance applications, such as data centers, servers, or high-speed storage systems. By intelligently managing memory access patterns, the method helps maintain consistent performance and reduce delays in data retrieval and storage operations.
26. A memory channel interleaving system for a power reduction or a performance improvement, the system comprising: a linear address remapping logic configured to remap a memory access address for two or more memory devices accessed via two or more respective memory ports with an interleaving access area and a linear access area, the interleaving access area comprising memory addresses for an interleaving access operation for the performance improvement, the linear access area comprising memory addresses for a linear access operation for the power reduction, a linear address remapping logic being configured to receive a signal that includes a power reduction mode or a performance improvement mode; and a memory controller configured to perform the interleaving access operation or the linear access operation according to the performance improvement mode or the power reduction mode.
This invention relates to a memory channel interleaving system designed to optimize power consumption or performance in computing systems. The system addresses the challenge of balancing power efficiency and performance in memory access operations, particularly in systems with multiple memory devices accessed via separate memory ports. The system includes a linear address remapping logic that remaps memory access addresses for two or more memory devices. The remapping logic divides the address space into two distinct areas: an interleaving access area and a linear access area. The interleaving access area contains memory addresses used for interleaving access operations, which improve performance by distributing memory requests across multiple memory devices. The linear access area contains memory addresses used for linear access operations, which reduce power consumption by concentrating memory requests on a single memory device. The linear address remapping logic receives a signal indicating whether the system should operate in a power reduction mode or a performance improvement mode. Based on this signal, a memory controller performs either the interleaving access operation (for performance improvement) or the linear access operation (for power reduction). This dynamic switching allows the system to adapt to different operational requirements, optimizing either power efficiency or performance as needed. The system is particularly useful in applications where memory access patterns vary, such as in mobile devices, embedded systems, or data centers.
27. The system of claim 26 , wherein a bandwidth balance among the two or more memory devices is adjusted through the interleaving access operation.
This invention relates to memory systems designed to optimize bandwidth utilization across multiple memory devices. The problem addressed is inefficient bandwidth distribution in systems with multiple memory devices, leading to bottlenecks and underutilization of available resources. The system includes a controller that manages data access operations across two or more memory devices, ensuring balanced bandwidth allocation. The controller performs interleaving access operations, where data requests are distributed across the memory devices in a coordinated manner to prevent any single device from becoming a performance bottleneck. By dynamically adjusting the interleaving pattern, the system maintains an optimal balance of bandwidth usage among the memory devices, improving overall system efficiency and performance. The interleaving access operation may involve distributing read and write requests, adjusting access timings, or reordering operations to ensure uniform workload distribution. This approach enhances data throughput and reduces latency by leveraging the combined bandwidth of all memory devices while avoiding overloading any individual device. The system is particularly useful in high-performance computing environments where memory bandwidth is a critical performance factor.
28. A system for providing a memory channel interleaving for a power reduction or a performance improvement, the system comprising: a system on chip (SOC) comprising linear address remapping logic configured to remap a memory access address for two or more memory devices accessed via two or more respective memory ports with an interleaving access area and a linear access area, the interleaving access area comprising memory addresses for an interleaving access operation for the performance improvement, the linear access area comprising memory addresses for a linear access operation for the power reduction, a linear address remapping logic being configured to receive a signal that includes a power reduction mode or a performance improvement mode; and a memory controller residing on the SoC and configured to perform the interleaving access operation or the linear access operation according to the performance improvement mode or the power reduction mode.
This invention relates to memory channel interleaving in system-on-chip (SoC) architectures to optimize power consumption or performance. The system addresses the challenge of balancing power efficiency and performance in memory access operations by dynamically adjusting memory address remapping. The SoC includes linear address remapping logic that remaps memory access addresses for multiple memory devices connected via separate memory ports. The remapping logic divides memory addresses into two regions: an interleaving access area for performance optimization and a linear access area for power reduction. The system receives a signal indicating whether to prioritize power reduction or performance improvement, and the memory controller executes the appropriate access operation accordingly. In performance mode, interleaving access operations distribute memory requests across multiple devices to enhance bandwidth and reduce latency. In power reduction mode, linear access operations consolidate requests to minimize active memory devices, lowering power consumption. The system dynamically switches between these modes based on operational requirements, providing flexibility in memory access strategies.
29. The system of claim 28 , wherein the linear access operation is performed in the linear access area with a first memory device among the two or more memory devices in the performance improvement mode and a second memory device among the two or more memory devices in the power reduction mode.
This invention relates to a memory system designed to optimize performance and power efficiency by dynamically adjusting operational modes of multiple memory devices. The system addresses the challenge of balancing high-speed data access with energy consumption in storage systems, particularly in scenarios where different memory devices may be used for different types of operations. The system includes two or more memory devices, each capable of operating in either a performance improvement mode or a power reduction mode. In the performance improvement mode, a memory device prioritizes faster data access, while in the power reduction mode, it conserves energy by reducing operational speed or power consumption. The system dynamically assigns these modes based on the type of data operation being performed. For linear access operations, which involve sequential data retrieval or storage, the system designates one memory device to operate in performance improvement mode to ensure rapid access, while another memory device operates in power reduction mode to save energy. This selective mode assignment allows the system to maintain high-speed performance for critical operations while minimizing unnecessary power usage for less demanding tasks. The system may also include additional features such as mode switching logic to dynamically adjust the operational modes of the memory devices based on real-time performance and power requirements.
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October 27, 2020
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