Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A display apparatus, comprising: a plurality of pixels arranged in a matrix; a plurality of scanning lines each connected to a group of pixels arranged in a row direction of the plurality of pixels; a plurality of data lines each connected to a group of pixels arranged in a column direction of the plurality of pixels; a scanning line drive unit to generate a scanning signal for selecting the group of pixels arranged in the row direction based on a scanning clock signal and successively output the generated scanning signal to the plurality of scanning lines, wherein the scanning clock signal indicates the drive timing of the plurality of scanning lines; a data line drive unit to output, to the plurality of data lines, data signals for supplying voltages to the group of pixels arranged in the row direction, wherein the group of pixels is selected by the scanning signal, and the voltages are based on video data; and a timing control unit to control the drive timing of the scanning line drive unit and the data line drive unit based on a first clock signal, and to generate the scanning clock signal based on the first clock signal; wherein the timing control unit comprises: a delay amount acquisition unit to acquire a delay amount at the time of level transition of the scanning clock signal relative to the time of level transition of a base timing signal, level transition from a first signal level to a second signal level of which is repeated in synchronization with the first clock signal at a period corresponding to one horizontal scanning period; a first timing generation unit to generate a first timing signal which delays the time of level transition of the base timing signal by a delay corresponding to a period unit of the first clock signal of the delay amount based on the first clock signal; a second timing generation unit to generate at least one second timing signal which delays the time of level transition of the first timing signal by a duration of a period unit of a second clock signal having frequency higher than frequency of the first clock signal; and a selection unit to output one timing signal as the scanning clock signal, wherein the one timing signal is selected from the first timing signal and the at least one second timing signal based on the delay amount.
2. The display apparatus according to claim 1 , wherein the delay amount acquisition unit acquires the delay amount for each of the plurality of scanning lines, the first timing signal generation unit delays the time of level transition indicating the drive timing of one scanning line in the base timing signal by a delay corresponding to the period unit of the first clock signal of the delay amount for the one scanning line to generate the first timing signal, and the selection unit outputs the one timing signal selected based on the delay amount for the one scanning line as a signal indicating the drive timing of the one scanning line in the scanning clock signal.
This invention relates to display apparatuses, specifically addressing timing control for driving scanning lines in a display panel. The problem solved is ensuring precise synchronization of drive signals across multiple scanning lines, particularly in high-resolution or high-speed displays where timing discrepancies can cause display artifacts. The apparatus includes a delay amount acquisition unit that determines a delay amount for each scanning line. A first timing signal generation unit then adjusts the timing of a base timing signal by applying a delay corresponding to the period of a first clock signal, based on the acquired delay amount for each scanning line. This generates a first timing signal with the corrected drive timing for each line. A selection unit then outputs the appropriate timing signal for each scanning line, ensuring that the scanning clock signal accurately reflects the required drive timing. The invention improves display uniformity by compensating for variations in signal propagation delays across different scanning lines, which is critical for maintaining image quality in advanced display technologies. The system dynamically adjusts timing to account for physical or electrical differences in the display panel, reducing distortions and enhancing synchronization.
3. The display apparatus according to claim 1 , further comprising a multiplication unit to multiply the first clock signal to generate the second clock signal.
A display apparatus includes a clock signal generator that produces a first clock signal and a second clock signal. The first clock signal is used to drive a display panel, while the second clock signal is used to drive a timing controller. The apparatus also includes a multiplication unit that multiplies the first clock signal to generate the second clock signal. This ensures synchronization between the display panel and the timing controller, improving display performance and reducing signal distortion. The multiplication unit allows the second clock signal to operate at a higher frequency than the first clock signal, enabling faster processing and more precise timing control. The apparatus may also include a phase adjustment unit to align the phases of the first and second clock signals, further enhancing synchronization. The display panel may be an organic light-emitting diode (OLED) panel or a liquid crystal display (LCD) panel, and the timing controller manages the display data and control signals. The multiplication unit ensures that the timing controller operates at an optimal frequency, improving overall display efficiency and reducing power consumption.
4. The display apparatus according to claim 1 , wherein the second timing signal generation unit comprises a serially-connected plurality of delay elements, and the at least one second timing signal comprises a plurality of second timing signals and the plurality of second timing signals respectively generated by the plurality of delay elements are input into the selection unit.
This invention relates to display apparatuses, specifically addressing timing signal generation for display control. The apparatus includes a timing signal generation unit that produces a first timing signal and a second timing signal generation unit that generates at least one second timing signal. The second timing signal generation unit contains a series of delay elements connected in sequence, each producing a distinct second timing signal. These multiple second timing signals are then fed into a selection unit, which chooses one or more of them based on a control signal. The selected timing signals are used to control display operations, such as pixel data processing or synchronization. The delay elements introduce controlled time shifts, allowing precise timing adjustments for display functions. This configuration enables flexible and accurate timing control, improving display performance by synchronizing operations with external signals or internal processing requirements. The invention is particularly useful in high-resolution or high-speed displays where precise timing is critical.
5. The display apparatus according to claim 4 , wherein the plurality of delay elements respectively delay signals input into the plurality of delay elements by one period of the second clock signal.
A display apparatus includes a signal processing circuit that generates a first clock signal and a second clock signal, where the second clock signal has a frequency that is a fraction of the first clock signal's frequency. The apparatus also includes a plurality of delay elements that receive input signals and delay these signals by one period of the second clock signal. These delayed signals are then used to control the display panel, ensuring synchronized operation. The delay elements help maintain timing accuracy by compensating for signal propagation delays, which is critical for high-resolution or high-refresh-rate displays. The apparatus may also include a phase detector that compares the phases of the first and second clock signals to adjust the delay elements dynamically, ensuring consistent performance. This design addresses timing mismatches in display driving circuits, improving image quality and reducing artifacts. The delay elements operate in synchronization with the second clock signal, ensuring precise signal alignment across the display panel.
6. The display apparatus according to claim 1 , wherein the first timing signal generation unit delays the base timing signal based on information obtained by rounding at least one less significant bit of information on the delay amount to generate the first timing signal.
A display apparatus includes a timing signal generation system that adjusts display synchronization. The apparatus addresses timing inaccuracies in display systems, particularly those caused by variations in signal propagation delays. The invention focuses on generating precise timing signals by refining a base timing signal using a delay adjustment mechanism. The apparatus includes a first timing signal generation unit that modifies the base timing signal by applying a controlled delay. The delay is determined by processing information on the required delay amount, specifically by rounding at least one less significant bit of the delay information. This rounding operation simplifies the delay calculation while maintaining sufficient precision for display synchronization. The resulting first timing signal is then used to control display operations, ensuring accurate timing alignment between different display components. The system may also include additional timing signal generation units that further refine the timing signals based on different delay adjustment techniques. These units work in conjunction to provide a robust timing control mechanism, compensating for variations in signal paths and component tolerances. The overall design improves display performance by reducing timing errors and enhancing synchronization between display elements.
7. The display apparatus according to claim 6 , wherein the selection unit selects the one timing signal based on information on the at least one less significant bit.
A display apparatus includes a timing signal selection unit that selects one timing signal from multiple available timing signals based on information from at least one less significant bit (LSB) of a digital signal. The apparatus generates multiple timing signals with different phases or frequencies, which are used to control display operations such as pixel data sampling, scanning, or synchronization. The selection unit evaluates the LSB information of a digital input signal, such as a video or control signal, to determine which timing signal should be used. This selection process ensures precise synchronization between the display's internal operations and the incoming signal, reducing timing errors and improving display quality. The apparatus may also include a phase adjustment unit that fine-tunes the selected timing signal to further optimize synchronization. By dynamically selecting timing signals based on LSB data, the display apparatus achieves higher accuracy in timing control, particularly for high-resolution or high-frequency signals where minor timing discrepancies can cause visual artifacts. This method enhances display performance by minimizing phase misalignment and signal distortion.
8. The display apparatus according to claim 1 , further comprising a horizontal counter unit and a vertical counter unit to respectively count the number of pulses of a horizontal synchronization signal and a vertical synchronization signal being in synchronization with video data corresponding to video to be displayed on a display panel comprising the plurality of pixels, wherein the delay amount acquisition unit acquires the delay amount based on the number of pulses of the horizontal synchronization signal and the vertical synchronization signal.
A display apparatus includes a display panel with multiple pixels and a delay amount acquisition unit that determines a delay amount for adjusting the timing of video data display. The apparatus further includes a horizontal counter unit and a vertical counter unit. The horizontal counter unit counts the number of pulses in a horizontal synchronization signal, while the vertical counter unit counts the number of pulses in a vertical synchronization signal. Both synchronization signals are synchronized with the video data intended for display. The delay amount acquisition unit uses the counted pulses of the horizontal and vertical synchronization signals to calculate the delay amount, ensuring proper synchronization and timing adjustments for the video data. This system helps maintain accurate display timing by dynamically adjusting for delays in signal processing, improving synchronization between the video data and the display panel's operation. The counters provide precise measurements of synchronization signal pulses, enabling the delay amount to be calculated based on real-time signal conditions. This approach enhances display performance by minimizing timing errors and ensuring smooth video playback.
9. A method of controlling a display apparatus, the display apparatus comprising: a plurality of pixels arranged in a matrix; a plurality of scanning lines each connected to a group of pixels arranged in a row direction of the plurality of pixels; a plurality of data lines each connected to a group of pixels arranged in a column direction of the plurality of pixels; a scanning line drive unit to generate a scanning signal for selecting the group of pixels arranged in the row direction based on a scanning clock signal and successively output the generated scanning signal to the plurality of scanning lines, wherein the scanning clock signal indicates the drive timing of the plurality of scanning lines; a data line drive unit to output, to the plurality of data lines, data signals for supplying voltages to the group of pixels arranged in the row direction, wherein the group of pixels is selected by the scanning signal, and the voltages are based on video data; and a timing control unit to control the drive timing of the scanning line drive unit and the data line drive unit based on a first clock signal, and to generate the scanning clock signal based on the first clock signal, the method of controlling a display apparatus comprising: acquiring a delay amount at the time of level transition of the scanning clock signal relative to the time of level transition of a base timing signal, level transition from a first signal level to a second signal level of which is repeated in synchronization with the first clock signal at a period corresponding to one horizontal scanning period; generating a first timing signal which delays the time of level transition of the base timing signal by a delay corresponding to a period unit of the first clock signal of the delay amount based on the first clock signal; generating at least one second timing signal which delays the time of level transition of the first timing signal by a duration of a period unit of a second clock signal having frequency higher than frequency of the first clock signal; and outputting one timing signal as the scanning clock signal, wherein the one timing signal is selected from the first timing signal and the at least one second timing signal based on the delay amount.
This invention relates to a method for controlling a display apparatus, specifically addressing timing synchronization issues in display driving circuits. The display apparatus includes a matrix of pixels, scanning lines connected to pixel rows, and data lines connected to pixel columns. A scanning line drive unit generates scanning signals to select pixel rows based on a scanning clock signal, while a data line drive unit supplies data signals to the selected rows based on video data. A timing control unit manages the drive timing of these units using a first clock signal and generates the scanning clock signal. The method involves acquiring a delay amount during level transitions of the scanning clock signal relative to a base timing signal, which transitions between two levels in sync with the first clock signal at a period matching one horizontal scanning period. A first timing signal is generated by delaying the base timing signal by a duration equivalent to the delay amount, measured in units of the first clock signal's period. At least one second timing signal is then created by further delaying the first timing signal by a duration equivalent to the period of a second clock signal, which has a higher frequency than the first clock signal. The scanning clock signal is output by selecting either the first timing signal or one of the second timing signals based on the delay amount. This approach ensures precise timing control, compensating for delays in the scanning clock signal to improve display synchronization and image quality.
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November 24, 2020
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