Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. An integrated device for generating a random signal, the integrated device comprising: a first terminal; a pulse signal generator configured to generate a current pulse train on the first terminal; and a first control circuit coupled to the first terminal and configured to convert the current pulse train into a voltage signal randomly comprising voltage pulses greater than a threshold, the random signal containing the voltage pulses greater than the threshold, wherein the integrated device is configured to receive the current pulse train at the first terminal and generate the random signal at the first terminal.
2. The integrated device according to claim 1 , further comprising a supply terminal configured to receive a supply voltage, wherein the first control circuit comprises a first MOS capacitor coupled between a first auxiliary voltage terminal, configured to deliver a first auxiliary voltage, and the first terminal, and wherein the first MOS capacitor is configured to generate a voltage pulse greater than the threshold in a presence of a current pulse in response to the first MOS capacitor reaching a depletion regime, the first control circuit being configured to charge and discharge the first MOS capacitor randomly.
This invention relates to integrated devices for managing voltage pulses in electronic circuits, particularly addressing the challenge of generating controlled voltage pulses that exceed a threshold voltage in response to current pulses. The device includes a supply terminal that receives a supply voltage and a first control circuit with a first MOS capacitor. The MOS capacitor is connected between a first auxiliary voltage terminal, which provides a first auxiliary voltage, and a first terminal. The MOS capacitor is designed to produce a voltage pulse greater than a specified threshold when a current pulse is applied, triggered by the capacitor entering a depletion regime. The control circuit randomly charges and discharges the MOS capacitor to ensure unpredictable voltage pulse generation, enhancing security or noise resilience in applications like random number generation or signal processing. The device may also include additional components, such as a second control circuit with a second MOS capacitor, to further refine pulse characteristics or enable differential operation. The random charging and discharging mechanism prevents predictable patterns, making the system suitable for secure or noise-sensitive applications.
3. The integrated device according to claim 2 , wherein the first auxiliary voltage terminal is the supply terminal, and wherein the first auxiliary voltage is the supply voltage.
This invention relates to integrated devices, particularly those involving voltage regulation and power management. The problem addressed is the need for efficient and reliable voltage distribution within integrated circuits, especially in systems requiring multiple voltage levels or auxiliary power paths. The device includes a main voltage terminal for receiving a primary supply voltage and at least one auxiliary voltage terminal for distributing an auxiliary voltage. The auxiliary voltage terminal is connected to the main voltage terminal through a switching element, allowing controlled voltage distribution. In this specific embodiment, the first auxiliary voltage terminal is directly connected to the supply terminal, meaning the auxiliary voltage is identical to the supply voltage. This configuration simplifies power routing by eliminating the need for additional voltage conversion or regulation, ensuring direct and efficient power delivery to components requiring the same voltage level as the main supply. The switching element ensures that the auxiliary voltage can be selectively enabled or disabled, providing flexibility in power management. This design is particularly useful in integrated circuits where certain components must operate at the same voltage as the main supply, reducing complexity and improving energy efficiency.
4. The integrated device according to claim 2 , further comprising a reference terminal configured to receive a reference voltage.
This invention relates to integrated devices for voltage regulation or signal processing, addressing the need for precise voltage control in electronic circuits. The device includes a reference terminal designed to receive a reference voltage, which serves as a stable baseline for comparison or regulation within the system. This reference voltage can be used to calibrate, stabilize, or condition signals, ensuring accurate performance in applications such as analog-to-digital conversion, voltage regulation, or sensor interfacing. The reference terminal may interface with an internal voltage reference generator or an external source, providing flexibility in system design. The device may also incorporate additional components, such as amplifiers, comparators, or feedback loops, to enhance functionality. By integrating the reference terminal, the device ensures consistent and reliable voltage levels, reducing errors and improving overall system accuracy. This solution is particularly useful in high-precision applications where voltage stability is critical, such as medical devices, industrial control systems, or communication circuits. The invention simplifies circuit design by consolidating voltage regulation and signal processing into a single integrated unit, reducing component count and improving efficiency.
5. The integrated device according to claim 4 , wherein the first control circuit further comprises: a main transistor coupled between the first terminal and a common node, wherein a substrate of the main transistor is coupled to the reference terminal by way of a second control circuit, and wherein the substrate of the main transistor is directly coupled to a gate of the main transistor; a second MOS capacitor coupled between the common node and a second auxiliary supply terminal configured to deliver a second auxiliary voltage; a first secondary transistor coupled between the first terminal and the reference terminal, wherein a gate of the first secondary transistor is coupled to the common node; a second secondary transistor coupled between the supply terminal and the common node, wherein a gate of the second secondary transistor is coupled to the gate of the main transistor; and a resistive element coupled between the common node and the reference terminal.
This invention relates to an integrated device for managing power supply and substrate biasing in semiconductor circuits, particularly addressing issues of voltage regulation and substrate noise coupling. The device includes a main transistor connected between a first terminal and a common node, with its substrate directly coupled to its gate and also connected to a reference terminal via a second control circuit. This configuration ensures stable substrate biasing and reduces noise interference. A second MOS capacitor is placed between the common node and a second auxiliary supply terminal, providing additional voltage regulation. The device also features two secondary transistors: one between the first terminal and the reference terminal, controlled by the common node, and another between the main supply terminal and the common node, controlled by the main transistor's gate. A resistive element between the common node and the reference terminal stabilizes the circuit. The design improves voltage stability, minimizes substrate noise, and enhances overall circuit reliability in integrated semiconductor applications.
6. The integrated device according to claim 5 , wherein the second auxiliary supply terminal is the supply terminal, and wherein the second auxiliary voltage is the reference voltage.
This invention relates to an integrated device designed to manage power distribution and voltage regulation within electronic systems. The device addresses the challenge of efficiently supplying and stabilizing multiple voltage levels in integrated circuits, particularly where precise voltage references are required for accurate operation. The integrated device includes a primary supply terminal and at least one auxiliary supply terminal, which can function as either a supply or reference voltage input. In this configuration, the second auxiliary supply terminal serves as the primary supply terminal, while the second auxiliary voltage acts as the reference voltage. This dual-functionality allows the device to dynamically adapt to different power management scenarios, ensuring stable voltage regulation and distribution across various components. The device also incorporates a voltage regulation mechanism that maintains the reference voltage at a consistent level, critical for applications requiring high precision, such as analog-to-digital converters or sensor interfaces. By integrating these functions, the device simplifies circuit design, reduces component count, and enhances reliability in power-sensitive applications. The flexible assignment of supply and reference roles optimizes power efficiency and performance in integrated systems.
7. The integrated device according to claim 5 , wherein the integrated device is disposed in a semiconductor substrate, and wherein an electrode of the first MOS capacitor and an electrode of the second MOS capacitor are produced in a same active zone of the semiconductor substrate.
This invention relates to integrated semiconductor devices, specifically addressing the challenge of efficiently implementing multiple MOS (Metal-Oxide-Semiconductor) capacitors in a compact semiconductor substrate. The device integrates at least two MOS capacitors within a single active zone of the semiconductor substrate, sharing a common electrode structure. This design minimizes space usage while maintaining independent functionality for each capacitor. The first MOS capacitor and the second MOS capacitor are formed adjacent to each other in the same active region, with their respective electrodes fabricated within this shared zone. The shared electrode configuration reduces the overall footprint of the device, making it suitable for high-density semiconductor applications. The invention leverages the semiconductor substrate's active zone to host multiple capacitors, optimizing layout efficiency without compromising electrical performance. This approach is particularly useful in integrated circuits where space constraints are critical, such as in memory cells, analog circuits, or RF (radio frequency) components. The shared active zone design simplifies manufacturing processes by reducing the number of distinct regions required for capacitor formation, thereby improving yield and reducing costs. The invention ensures that each MOS capacitor operates independently despite sharing the same active zone, maintaining the required electrical isolation and functionality.
8. The integrated device according to claim 7 , wherein the electrode of the first MOS capacitor and the electrode of the second MOS capacitor are spatially juxtaposed with respective electrode semiconductor regions of the main transistor, the respective electrode semiconductor regions comprising a drain semiconductor region and a source semiconductor region, and wherein the first terminal contacts the drain semiconductor region of the main transistor.
This invention relates to integrated semiconductor devices, specifically focusing on the spatial arrangement of MOS (Metal-Oxide-Semiconductor) capacitors and a main transistor within a single integrated circuit. The problem addressed is optimizing the layout and electrical connectivity of these components to improve performance and efficiency in semiconductor devices. The device includes a main transistor with source and drain semiconductor regions, along with two MOS capacitors. The electrodes of these capacitors are positioned adjacent to the source and drain regions of the main transistor. The first terminal of the device is electrically connected to the drain semiconductor region of the main transistor. This configuration ensures close proximity between the capacitors and the transistor, reducing parasitic effects and improving signal integrity. The spatial juxtaposition of the electrodes with the transistor's semiconductor regions enhances the device's compactness and operational efficiency. The invention is particularly useful in high-density integrated circuits where minimizing footprint and optimizing electrical performance are critical.
9. The integrated device according to claim 7 , wherein the semiconductor substrate is of a silicon-on-insulator type.
The invention relates to integrated devices, specifically those incorporating a semiconductor substrate. The problem addressed is improving the performance and efficiency of integrated circuits by utilizing a silicon-on-insulator (SOI) substrate. SOI technology enhances device isolation, reduces parasitic capacitance, and improves high-frequency performance compared to traditional bulk silicon substrates. The integrated device includes a semiconductor substrate, which in this embodiment is of a silicon-on-insulator type. The SOI substrate consists of a thin silicon layer on top of an insulating layer, typically silicon dioxide, which is itself on a bulk silicon wafer. This structure provides better electrical insulation between devices, reducing leakage currents and improving power efficiency. The device further includes a first conductive layer formed on the semiconductor substrate, a second conductive layer formed on the first conductive layer, and a third conductive layer formed on the second conductive layer. These layers are electrically connected to form a functional circuit, such as a transistor or memory cell. The use of an SOI substrate in this configuration enhances the device's speed, reduces power consumption, and improves reliability by minimizing interference between adjacent components. This technology is particularly useful in high-performance computing, RF applications, and low-power electronics.
10. The integrated device according to claim 5 , wherein the resistive element has a resistance greater than one megaohm.
The invention relates to an integrated device designed for high-resistance applications, addressing the need for precise and stable resistance values in electronic circuits. The device includes a resistive element with a resistance greater than one megaohm, ensuring minimal current leakage and high accuracy in signal processing. This high-resistance feature is particularly useful in applications requiring low-power consumption, such as sensor interfaces, analog-to-digital converters, or precision measurement systems. The resistive element is integrated into a semiconductor substrate, allowing for compact and scalable fabrication. The device may also include additional components, such as transistors or capacitors, to enhance functionality. The high-resistance characteristic ensures reliable performance in environments where signal integrity and power efficiency are critical. The invention provides a solution for integrating high-resistance elements into semiconductor devices without compromising performance or manufacturability.
11. The integrated device according to claim 5 , wherein the second control circuit comprises a control resistor.
This invention relates to an integrated device for managing power distribution in electronic systems, particularly addressing the challenge of efficiently controlling power flow between multiple power sources and loads while maintaining stability and reliability. The device includes a first control circuit that regulates power distribution from a primary power source to a load, ensuring stable voltage and current delivery. A second control circuit, connected to a secondary power source, further enhances power management by dynamically adjusting power flow based on system demands. The second control circuit incorporates a control resistor, which acts as a variable impedance element to fine-tune power distribution, preventing overcurrent conditions and improving energy efficiency. The integrated device also includes a monitoring circuit that continuously tracks voltage, current, and temperature, providing real-time feedback to the control circuits for adaptive adjustments. This ensures optimal performance under varying load conditions and environmental factors. The control resistor in the second circuit allows precise modulation of power transfer, reducing losses and enhancing system responsiveness. The overall design aims to provide a robust, efficient power management solution for applications requiring high reliability, such as industrial equipment, automotive systems, and renewable energy integration.
12. The integrated device according to claim 5 , wherein the second control circuit comprises a control transistor comprising a control electrode configured to receive a control signal so as to modify a resistance of a drain-source connection of the control transistor.
This invention relates to an integrated device for controlling electrical resistance in a circuit. The device addresses the need for precise and adjustable resistance modulation in integrated circuits, particularly in applications requiring dynamic impedance control, such as power management, signal conditioning, or sensor interfacing. The integrated device includes a control circuit with a control transistor that regulates resistance across its drain-source connection. The control transistor has a control electrode, such as a gate, which receives a control signal to adjust the resistance. By varying the control signal, the transistor's resistance can be dynamically modified, enabling precise control over current flow or voltage division in the circuit. This feature is useful for applications where resistance needs to be tuned in real-time, such as adaptive biasing, impedance matching, or load regulation. The control circuit may also include additional components, such as a reference voltage generator or a feedback loop, to ensure stable and accurate resistance modulation. The device is designed to be compact and efficient, making it suitable for integration into modern semiconductor systems where space and power efficiency are critical. The ability to adjust resistance electronically, rather than through passive components, provides greater flexibility and performance in integrated circuit designs.
13. The integrated device according to claim 1 , wherein the first control circuit comprises a main transistor, a first MOS capacitor, and a second MOS capacitor disposed over a buried oxide layer of a semiconductor substrate.
This invention relates to integrated semiconductor devices, specifically addressing the need for improved control circuits in semiconductor substrates with buried oxide layers. The device includes a first control circuit featuring a main transistor and two MOS (metal-oxide-semiconductor) capacitors, all disposed over a buried oxide layer of a semiconductor substrate. The main transistor functions as a switching or amplifying element, while the first and second MOS capacitors provide capacitive coupling for signal processing or charge storage. The buried oxide layer electrically isolates the active components from the underlying substrate, reducing leakage and enhancing performance. This configuration is particularly useful in applications requiring high-speed switching, low-power operation, or precise signal control, such as in RF (radio frequency) circuits, memory devices, or analog/digital interfaces. The integration of the transistor and capacitors over the buried oxide layer optimizes space efficiency and electrical isolation, improving overall device reliability and performance. The invention addresses challenges in semiconductor design where traditional bulk substrates may introduce unwanted parasitic effects or performance limitations.
14. The integrated device according to claim 13 , wherein a first plate of the first MOS capacitor is coupled to a supply terminal configured to receive a supply voltage, a first plate of the second MOS capacitor is coupled to the supply terminal, a second plate of the first MOS capacitor is coupled to a drain of the main transistor and the first terminal, a second plate of the second MOS capacitor is coupled to a source of the main transistor.
This invention relates to an integrated device with a main transistor and two MOS capacitors for voltage regulation or signal processing. The device includes a main transistor with a drain, source, and gate, and two MOS capacitors. The first MOS capacitor has a first plate connected to a supply terminal receiving a supply voltage and a second plate connected to the drain of the main transistor and a first terminal of the device. The second MOS capacitor has a first plate also connected to the supply terminal and a second plate connected to the source of the main transistor. The configuration allows the capacitors to interact with the main transistor to control voltage levels or signal behavior, potentially improving performance or stability in integrated circuits. The device may be used in applications requiring precise voltage regulation, signal conditioning, or power management, where the MOS capacitors help manage voltage distribution across the main transistor. The arrangement ensures efficient coupling between the supply voltage and the transistor terminals, enabling dynamic adjustments to voltage or current flow. This setup can enhance the device's ability to handle varying load conditions or signal variations while maintaining desired electrical characteristics.
15. The integrated device according to claim 13 , wherein the integrated device is disposed in the semiconductor substrate, and wherein an electrode of the first MOS capacitor and an electrode of the second MOS capacitor are produced in a same active zone of the semiconductor substrate.
This invention relates to semiconductor devices, specifically integrated circuits incorporating metal-oxide-semiconductor (MOS) capacitors. The problem addressed is the need for compact, high-performance integrated devices that minimize area usage while maintaining reliable electrical characteristics. The invention describes an integrated device formed within a semiconductor substrate, where two MOS capacitors share a common active zone. Each MOS capacitor includes a gate electrode, a dielectric layer, and a semiconductor channel region. The first and second MOS capacitors are fabricated such that their respective electrodes are produced within the same active zone of the substrate, reducing the overall footprint compared to traditional designs where separate active zones are used for each capacitor. This shared active zone configuration allows for tighter integration, improving space efficiency in semiconductor layouts. The device may also include additional components, such as transistors or other passive elements, depending on the specific application. The shared active zone design ensures that the electrical properties of the capacitors remain consistent while optimizing the use of substrate area. This approach is particularly useful in high-density integrated circuits where minimizing space is critical, such as in memory cells, analog circuits, or mixed-signal systems. The invention provides a solution for reducing the physical size of integrated circuits without compromising performance or reliability.
16. A system comprising: at least one integrated device for generating a random signal, the at least one integrated device comprising: a first terminal; a pulse signal generator configured to generate a current pulse train on the first terminal; and a first control circuit coupled to the first terminal and configured to convert the current pulse train into a voltage signal randomly comprising voltage pulses greater than a threshold, the random signal containing the voltage pulses greater than the threshold, the system being a random counter comprising a plurality of flip-flops having clock inputs coupled to the first terminal of the at least one integrated device.
This invention relates to a random signal generation system, specifically a random counter, designed to produce unpredictable voltage pulses for applications requiring randomness, such as cryptography or testing. The system addresses the need for reliable, hardware-based random signal generation without relying on external noise sources or complex algorithms. The system includes at least one integrated device that generates a random signal through a combination of a pulse signal generator and a control circuit. The pulse signal generator produces a current pulse train on a first terminal, which is then processed by the control circuit. The control circuit converts the current pulses into a voltage signal, where only pulses exceeding a predefined threshold are retained, ensuring randomness in the output. This voltage signal, containing the randomly selected pulses, serves as the random signal. The system integrates this random signal into a random counter, which consists of multiple flip-flops. The clock inputs of these flip-flops are connected to the first terminal of the integrated device, meaning they are driven by the random voltage pulses. This setup ensures that the counter operates in an unpredictable manner, suitable for applications requiring true randomness. The design avoids deterministic patterns, making it useful for security-sensitive environments.
17. The system according to claim 16 , wherein the first control circuit comprises a main transistor, a first MOS capacitor, and a second MOS capacitor disposed over a buried oxide layer of a semiconductor substrate, and wherein an electrode of the first MOS capacitor and an electrode of the second MOS capacitor are produced in a same active zone of the semiconductor substrate.
This invention relates to semiconductor systems, specifically integrated circuits with improved control circuitry for managing power and signal processing. The system addresses challenges in miniaturization and efficiency by integrating multiple components within a compact layout while maintaining performance. The system includes a first control circuit with a main transistor and two MOS capacitors, all fabricated over a buried oxide layer on a semiconductor substrate. The main transistor functions as a switching or amplifying element, while the MOS capacitors provide charge storage or coupling functions. Both MOS capacitors share a common active zone in the substrate, meaning their electrodes are formed within the same semiconductor region. This shared active zone reduces layout area and improves integration density. The buried oxide layer electrically isolates the components from the substrate, reducing leakage and noise. The first MOS capacitor and second MOS capacitor may be configured for different voltage or signal handling roles, such as decoupling, filtering, or dynamic threshold modulation. The main transistor and capacitors are interconnected to form a functional unit, such as a power management circuit, analog signal processor, or memory cell. The design optimizes space efficiency by reusing the active zone for multiple components, which is particularly useful in advanced semiconductor nodes where area constraints are critical. The system may be part of a larger integrated circuit, such as a microcontroller, RF transceiver, or memory device, where compact and efficient control circuitry is essential.
18. A system comprising: at least one integrated device for generating a random signal, the at least one integrated device comprising: a first terminal; a pulse signal generator configured to generate a current pulse train on the first terminal; a first control circuit coupled to the first terminal and configured to convert the current pulse train into a voltage signal randomly comprising voltage pulses greater than a threshold, the random signal containing the voltage pulses greater than the threshold; and a plurality of integrated devices, the system being a random number generator comprising a plurality of flip-flops, each flip-flop having a data input coupled to a respective integrated device of the plurality of integrated devices.
This invention relates to a random number generator system designed to produce high-quality random signals for cryptographic or statistical applications. The system addresses the challenge of generating true randomness in integrated circuits, where deterministic noise sources can compromise security and reliability. The core of the system is an integrated device that generates a random signal by converting a current pulse train into a voltage signal containing random voltage pulses exceeding a predefined threshold. The pulse signal generator produces a current pulse train on a terminal, while a control circuit processes this train to extract random voltage pulses. Multiple such integrated devices are used in parallel, each feeding into a flip-flop circuit. The flip-flops sample the random signals at their data inputs, producing a final random output. This architecture leverages physical randomness from the pulse train conversion process, ensuring unpredictability. The system is scalable, with multiple integrated devices and flip-flops working together to enhance randomness quality and throughput. The design avoids reliance on pseudo-random algorithms, providing a hardware-based solution for secure random number generation.
19. The system according to claim 18 , wherein the first control circuit comprises a main transistor, a first MOS capacitor, and a second MOS capacitor disposed over a buried oxide layer of a semiconductor substrate, and wherein an electrode of the first MOS capacitor and an electrode of the second MOS capacitor are produced in a same active zone of the semiconductor substrate.
This invention relates to semiconductor systems, specifically integrated circuits with improved control circuitry for managing power and signal processing. The system addresses challenges in miniaturization and efficiency by integrating multiple components within a compact structure while maintaining performance. The system includes a first control circuit with a main transistor and two MOS (Metal-Oxide-Semiconductor) capacitors. These components are fabricated over a buried oxide layer on a semiconductor substrate, enhancing insulation and reducing leakage. The main transistor functions as a switching or amplifying element, while the MOS capacitors provide charge storage or coupling capabilities. A key innovation is that the electrodes of both MOS capacitors are formed within the same active zone of the substrate, optimizing space and reducing parasitic effects. This design allows for tighter integration, lower power consumption, and improved signal integrity in advanced semiconductor devices. The system is particularly useful in applications requiring high-density, low-power integrated circuits, such as microprocessors, memory chips, or RF (radio frequency) circuits.
20. An integrated device for generating a random signal, the integrated device comprising: a first terminal; a supply terminal configured to receive a supply voltage a pulse signal generator configured to generate a current pulse train on the first terminal; a first control circuit coupled to the first terminal and configured to convert the current pulse train into a voltage signal randomly comprising voltage pulses greater than a threshold, the random signal containing the voltage pulses greater than the threshold, wherein the first control circuit comprises a first MOS capacitor coupled between a first auxiliary supply terminal configured to deliver a first auxiliary voltage and the first terminal; a main transistor coupled between the first terminal and a common node, wherein a substrate of the main transistor is coupled to a reference terminal, configured to receive a reference voltage, by way of a second control circuit, and wherein the substrate of the main transistor is directly coupled to a gate of the main transistor; a second MOS capacitor coupled between the common node and a second auxiliary supply terminal configured to deliver a second auxiliary voltage; a first secondary transistor coupled between the first terminal and the reference terminal, wherein a gate of the first secondary transistor is coupled to the common node; a second secondary transistor coupled between the supply terminal and the common node, wherein a gate of the second secondary transistor is coupled to the gate of the main transistor; and a resistive element coupled between the common node and the reference terminal.
This invention relates to an integrated circuit for generating a random signal, addressing the need for reliable random signal generation in electronic systems. The device includes a pulse signal generator that produces a current pulse train on a first terminal. A control circuit converts this current pulse train into a voltage signal containing random voltage pulses exceeding a predefined threshold. The control circuit features a MOS capacitor connected between an auxiliary supply terminal and the first terminal, enabling voltage modulation. A main transistor is coupled between the first terminal and a common node, with its substrate directly connected to its gate and linked to a reference terminal via a second control circuit. This configuration ensures substrate bias control, influencing transistor behavior. A second MOS capacitor connects the common node to another auxiliary supply terminal, further modulating voltage levels. Two secondary transistors are used: one between the first terminal and the reference terminal, controlled by the common node, and another between the supply terminal and the common node, controlled by the main transistor's gate. A resistive element between the common node and the reference terminal stabilizes the circuit. The interaction of these components generates a random voltage signal by leveraging noise and transistor characteristics, providing a compact and efficient solution for random signal generation in integrated circuits.
21. The integrated device according to claim 20 , wherein the integrated device is disposed in a semiconductor substrate, and wherein an electrode of the first MOS capacitor and an electrode of the second MOS capacitor are disposed in a same active zone of the semiconductor substrate.
This invention relates to integrated semiconductor devices, specifically an integrated device with two MOS (Metal-Oxide-Semiconductor) capacitors sharing a common active zone in a semiconductor substrate. The device addresses the challenge of miniaturization in semiconductor manufacturing by optimizing space efficiency while maintaining functional separation between the capacitors. The integrated device includes a first MOS capacitor and a second MOS capacitor, both formed within the same semiconductor substrate. Each capacitor comprises a gate electrode, a dielectric layer, and a semiconductor channel region. The key innovation is that one electrode of the first MOS capacitor and one electrode of the second MOS capacitor are positioned within the same active zone of the substrate. This shared active zone reduces the overall footprint of the device, enabling higher integration density in semiconductor circuits. The device may further include additional components such as transistors or other passive elements, which can be integrated alongside the capacitors to form a compact circuit module. The shared active zone configuration ensures electrical isolation between the capacitors while minimizing layout area, making it suitable for advanced semiconductor processes where space constraints are critical. This design is particularly useful in analog and mixed-signal circuits where multiple capacitors are required in close proximity.
22. The integrated device according to claim 21 , wherein the electrode of the first MOS capacitor and the electrode of the second MOS capacitor are spatially adjacent to respective electrode semiconductor regions of the main transistor, the respective electrode semiconductor regions comprising a drain semiconductor region and a source semiconductor region, and wherein the first terminal contacts the drain semiconductor region of the main transistor.
This invention relates to integrated semiconductor devices, specifically focusing on the spatial arrangement of MOS (Metal-Oxide-Semiconductor) capacitors and their integration with a main transistor. The problem addressed is optimizing the layout and electrical connectivity of MOS capacitors in close proximity to the main transistor's source and drain regions to improve performance and efficiency in semiconductor circuits. The device includes a main transistor with source and drain semiconductor regions, along with two MOS capacitors. The electrodes of these capacitors are positioned adjacent to the transistor's source and drain regions. The first terminal of the device is electrically connected to the drain region of the main transistor. The second MOS capacitor's electrode is adjacent to the source region, while the first MOS capacitor's electrode is adjacent to the drain region. This spatial arrangement ensures efficient charge storage and transfer, reducing parasitic effects and improving circuit functionality. The integration of these components in a compact layout enhances the device's overall performance by minimizing signal delays and power consumption. The invention is particularly useful in high-density semiconductor applications where space efficiency and electrical performance are critical.
23. The integrated device according to claim 20 , wherein the first MOS capacitor is configured to generate a voltage pulse greater than the threshold in a presence of a current pulse in response to the first MOS capacitor reaching a depletion regime, the first control circuit being configured to charge and discharge the first MOS capacitor randomly.
This invention relates to an integrated device featuring a metal-oxide-semiconductor (MOS) capacitor configured to generate a voltage pulse exceeding a predefined threshold when a current pulse is applied, specifically when the MOS capacitor enters a depletion regime. The device includes a control circuit that randomly charges and discharges the MOS capacitor, enabling unpredictable voltage pulse generation. The MOS capacitor operates in a depletion mode, where the applied current pulse triggers a voltage spike beyond the threshold, useful for applications requiring random or stochastic behavior. The control circuit manages the charging and discharging processes to ensure randomness, preventing predictable patterns in the voltage output. This design is particularly applicable in circuits requiring random signal generation, such as in cryptographic systems, noise generation, or stochastic computing. The randomness in the voltage pulses is achieved through the uncontrolled transition into depletion, combined with the random charging and discharging cycles controlled by the circuit. The device leverages the inherent properties of MOS capacitors in depletion to produce unpredictable voltage responses, enhancing security or variability in electronic systems.
24. The integrated device according to claim 20 , wherein the resistive element has a resistance greater than one megaohm.
This invention relates to an integrated device designed for high-resistance applications, addressing the need for precise and stable resistance values in electronic circuits. The device includes a resistive element with a resistance greater than one megaohm, ensuring minimal current leakage and high accuracy in signal processing. The resistive element is integrated into a semiconductor substrate, allowing for compact and efficient circuit design. The high-resistance characteristic is achieved through material selection, doping concentration, or structural modifications, ensuring reliability across varying environmental conditions. The device may be used in applications such as analog signal conditioning, sensor interfaces, or precision measurement systems where low current consumption and high impedance are critical. The integration of the resistive element with other circuit components on a single substrate reduces parasitic effects and improves overall performance. The invention provides a solution for applications requiring stable, high-resistance components in integrated circuits, enhancing functionality in sensitive electronic systems.
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December 1, 2020
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