Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. An asynchronous data capture device, comprising: an edge spread detector circuit configured to: receive a data stream; identify transitions in the data stream; determine a sampling point based on the identified transitions in the data stream; a clock generator coupled to the edge spread detector circuit and configured to: adjust a phase offset based on the sampling point, and generate a clock signal having the adjusted phase offset; and a data sampling circuit coupled to the clock generator and configured to: sample the data stream at the sampling point.
This invention relates to asynchronous data capture devices used in high-speed data communication systems. The problem addressed is the accurate sampling of data streams where timing misalignment between the data and clock signals can lead to errors. Traditional synchronous systems rely on fixed clock phases, which may not align optimally with incoming data transitions, especially in noisy or variable environments. The device includes an edge spread detector circuit that receives a data stream and identifies transitions within it. By analyzing these transitions, the circuit determines an optimal sampling point for the data. A clock generator, coupled to the edge spread detector, adjusts the phase offset of a clock signal based on the determined sampling point. This ensures the clock signal aligns precisely with the data transitions. Finally, a data sampling circuit, connected to the clock generator, samples the data stream at the adjusted sampling point, improving data accuracy. The edge spread detector circuit dynamically tracks data transitions, allowing the system to adapt to varying data rates or signal distortions. The clock generator's phase adjustment mechanism compensates for timing mismatches, while the data sampling circuit ensures reliable data capture. This asynchronous approach enhances performance in environments where synchronous clocking is impractical or error-prone. The invention is particularly useful in high-speed serial communication, signal processing, and systems requiring precise timing alignment.
2. The data capture device of claim 1 , wherein the clock generator is configured to adjust the phase offset based on the sampling point such that the clock signal has a rising edge at the sampling point.
A data capture device is used in high-speed communication systems to accurately sample incoming data signals. The device includes a clock generator that produces a clock signal synchronized with the data signal. The clock generator adjusts the phase offset of the clock signal to ensure that the rising edge of the clock signal aligns precisely with the optimal sampling point of the data signal. This alignment minimizes sampling errors and improves data integrity, particularly in systems where signal timing variations or noise could otherwise degrade performance. The phase adjustment is dynamically controlled to compensate for variations in the data signal's timing, ensuring consistent and reliable data capture. The device may also include additional components, such as a phase detector and a loop filter, to refine the clock signal's phase alignment further. By dynamically adjusting the clock signal's phase, the data capture device enhances the accuracy and reliability of data sampling in high-speed communication applications.
3. The data capture device of claim 1 , wherein the edge spread detector circuit is configured to determine the sampling point such that the sampling point is isolated from the identified transitions.
A data capture device is designed to improve signal integrity in high-speed data transmission systems, particularly where signal distortion and noise can degrade performance. The device includes an edge spread detector circuit that analyzes the received signal to identify transitions between signal levels. These transitions often introduce noise and distortion, making accurate data sampling challenging. The edge spread detector circuit determines an optimal sampling point by ensuring it is isolated from these identified transitions. This isolation minimizes the impact of transition-related noise and distortion, improving the accuracy and reliability of data capture. The device may also include additional components such as a phase-locked loop (PLL) or a delay-locked loop (DLL) to further refine timing and synchronization. By dynamically adjusting the sampling point based on real-time signal analysis, the device enhances data recovery in high-speed communication systems, reducing errors and improving overall system performance. The invention is particularly useful in applications where signal integrity is critical, such as in high-speed serial data links, optical communication systems, and other environments with significant signal degradation.
4. The data capture device of claim 1 , wherein the edge spread detector circuit comprises: an edge detector sub-circuit configured to receive the data stream and identify transitions in the data stream; and a shift register coupled to the edge detector sub-circuit.
The invention relates to data capture devices, specifically those used in high-speed data transmission systems where signal integrity and accurate data recovery are critical. A common problem in such systems is the detection of edge transitions in a data stream, which is essential for synchronizing the receiver and recovering the transmitted data accurately. Traditional methods may suffer from inaccuracies due to noise, jitter, or signal distortion, leading to errors in data interpretation. The invention addresses this problem by incorporating an edge spread detector circuit within the data capture device. This circuit includes an edge detector sub-circuit that receives the data stream and identifies transitions, such as rising or falling edges, within the signal. The edge detector sub-circuit processes the incoming data stream to detect these transitions with high precision, ensuring reliable synchronization. Coupled to the edge detector sub-circuit is a shift register, which stores the detected transitions. The shift register allows for further processing, such as filtering or timing adjustments, to enhance the accuracy of edge detection and improve overall system performance. By integrating these components, the invention provides a robust solution for detecting and managing edge transitions in high-speed data streams, reducing errors and improving data recovery efficiency.
5. The data capture device of claim 4 , wherein the shift register comprises a cyclic shift register.
A data capture device is designed to efficiently process and store digital signals, particularly in applications requiring high-speed data acquisition. The device addresses challenges in traditional data capture systems, such as limited storage capacity and inefficient data handling, by incorporating a shift register with enhanced functionality. The shift register is configured as a cyclic shift register, enabling continuous data circulation without loss. This cyclic operation allows the device to retain data indefinitely or until manually cleared, improving reliability in applications where data retention is critical. The shift register can also be reset to a predefined state, ensuring consistent operation. The device further includes a data input interface to receive digital signals and a control unit to manage data flow, including shifting and resetting operations. The cyclic shift register's ability to loop data makes it particularly useful in systems requiring real-time monitoring, signal processing, or buffering, such as in telecommunications, industrial automation, or digital signal processing. The device's modular design allows integration into larger systems while maintaining high performance and flexibility.
6. The data capture device of claim 4 , wherein the edge detector sub-circuit comprises: a first flip flop having an input configured to receive the data stream; a second flip flop coupled to the first flip flop; a first logic gate coupled to the first and the second flip flops; and a second logic gate coupled to the first logic gate and an output of the shift register.
This invention relates to a data capture device with an edge detector sub-circuit designed to detect transitions in a data stream. The device addresses the challenge of accurately identifying rising or falling edges in digital signals, which is critical for synchronization and data recovery in communication systems. The edge detector sub-circuit includes a first flip-flop that receives the input data stream and a second flip-flop connected to the first. A first logic gate, such as an XOR gate, is coupled to both flip-flops to compare their outputs and detect changes in the data stream. A second logic gate, such as an AND or OR gate, is connected to the first logic gate and the output of a shift register. The shift register may be used to delay or buffer the data stream for further processing. The combination of flip-flops and logic gates enables precise edge detection by comparing current and previous states of the data stream, ensuring reliable signal processing in high-speed applications. This design improves the accuracy and efficiency of data capture systems by minimizing false edge detections and enhancing synchronization.
7. The data capture device of claim 6 , wherein the first logic gate is an XOR logic gate.
A data capture device is designed to process and analyze digital signals, particularly in systems where signal integrity and error detection are critical. The device includes a logic gate that compares input signals to detect discrepancies or changes, ensuring accurate data transmission and processing. In this configuration, the logic gate is specifically an XOR (exclusive OR) gate, which outputs a true signal only when the input signals differ. This setup is useful in applications such as error detection, parity checking, or signal synchronization, where identifying mismatches between input signals is essential. The XOR gate's ability to highlight differences between binary inputs makes it particularly effective for these purposes. The device may also include additional components, such as signal conditioning circuits or processing units, to further enhance signal analysis and reliability. By incorporating an XOR gate, the device ensures robust detection of signal variations, improving overall system performance in digital communication and data processing applications.
8. The data capture device of claim 6 , wherein the second logic gate is an OR logic gate.
A data capture device is designed to process and analyze input signals, particularly in applications requiring high-speed or real-time data acquisition. The device includes multiple logic gates to condition and route signals for further processing. Specifically, the device incorporates a second logic gate that functions as an OR logic gate. This OR gate combines multiple input signals into a single output signal, activating the output if any of the input signals are active. The OR logic gate enhances the device's ability to detect and respond to multiple concurrent or sequential input conditions, improving signal processing efficiency and reliability. The device may also include additional logic gates, such as AND gates, to perform complementary operations like requiring all input signals to be active before generating an output. The OR gate's configuration allows the device to handle complex signal combinations, making it suitable for applications in digital signal processing, control systems, and data acquisition where flexible signal routing and conditional logic are essential. The overall design ensures robust signal handling while maintaining low latency and high accuracy in data capture operations.
9. A device comprising: a data terminal; a first clock generator; an edge spread detector circuit having an input coupled to the data terminal and having a clock input coupled to an output of the first clock generator; a second clock generator having an input coupled to an output of the edge spread detector circuit and having an output to provide a clock signal with an adjusted phase offset, wherein the second clock generator is configured to adjust the phase offset based on the output of the edge spread detector circuit; and a data capture circuit having a first input coupled to the data terminal and having a clock input coupled to an output of the second clock generator, the data capture circuit having a data output.
This invention relates to data communication systems, specifically addressing timing synchronization challenges in high-speed data transmission. The device improves signal integrity by dynamically adjusting clock phase alignment to compensate for edge spreading, a common issue in high-frequency data signals where signal edges become distorted due to transmission line effects or noise. The device includes a data terminal for receiving incoming data signals, a first clock generator to produce a reference clock, and an edge spread detector circuit that analyzes the incoming data for edge distortions. The detector's output is fed to a second clock generator, which adjusts the phase of its output clock signal based on the detected edge spread. This adjusted clock signal is then used by a data capture circuit to sample the incoming data at optimal points, minimizing errors caused by misaligned timing. The system ensures reliable data recovery by dynamically compensating for varying edge conditions, enhancing performance in high-speed communication links. The invention is particularly useful in applications where signal integrity is critical, such as serial data interfaces or high-frequency digital systems.
10. The device of claim 9 , wherein the first clock generator is configured to output a first clock signal with a first clock frequency.
A system for generating and distributing clock signals in electronic circuits addresses timing synchronization challenges in high-speed digital systems. The system includes a first clock generator that produces a first clock signal with a specified frequency. This clock signal is used to synchronize operations across multiple components, ensuring precise timing for data processing, communication, and control functions. The system may also incorporate additional clock generators to produce secondary clock signals with different frequencies or phases, enabling flexible timing control for various subsystems. These clock signals are distributed through a network of interconnects, which may include buffers, phase-locked loops (PLLs), or delay-locked loops (DLLs) to maintain signal integrity and minimize skew. The system is particularly useful in applications requiring high-frequency operation, such as microprocessors, field-programmable gate arrays (FPGAs), and communication devices, where accurate timing is critical for performance and reliability. The design ensures low-jitter clock distribution, reducing timing errors and improving overall system efficiency.
11. The device of claim 10 , wherein the second clock generator is configured to output the clock signal with a second clock frequency, and wherein the first clock frequency is a multiple of the second clock frequency.
This invention relates to clock signal generation in electronic systems, specifically addressing the need for synchronized clock signals with precise frequency relationships. The device includes a first clock generator producing a clock signal at a first frequency and a second clock generator producing a second clock signal at a second frequency. The second frequency is a multiple of the first frequency, ensuring a fixed phase and frequency relationship between the two signals. This synchronization is critical for applications requiring precise timing, such as digital signal processing, communication systems, or synchronized data transfer. The device may also include a phase detector to compare the phases of the two clock signals and adjust the second clock generator to maintain the desired frequency relationship. The first clock generator may be a reference oscillator, while the second clock generator could be a phase-locked loop (PLL) or a frequency divider. The invention ensures stable, synchronized clock signals with minimal phase noise, improving system performance in high-speed digital circuits. The fixed frequency ratio between the two signals simplifies timing management in complex electronic systems.
12. The device of claim 11 , wherein the second clock frequency corresponds to a clock frequency for a data stream received by the data terminal.
A system for managing clock synchronization in a data communication terminal is disclosed. The system addresses the challenge of maintaining accurate timing in data terminals that process multiple data streams with different clock frequencies. The invention includes a clock synchronization circuit that dynamically adjusts its operation based on the clock frequency of an incoming data stream. The circuit generates a second clock frequency that matches the frequency of the data stream received by the data terminal, ensuring precise timing alignment. This synchronization is critical for reliable data transmission and reception, particularly in high-speed communication systems where timing errors can lead to data corruption or loss. The system may also include a phase-locked loop (PLL) or other clock generation circuitry to produce the second clock frequency, which is then used to synchronize internal operations of the data terminal with the incoming data stream. The invention improves communication reliability by reducing timing mismatches between the terminal and external data sources.
13. The device of claim 9 , wherein the output of the edge spread detector circuit comprises a sampling point.
A system for detecting and analyzing edge spread in signals, particularly in high-speed data transmission or imaging applications, addresses the challenge of accurately identifying and quantifying signal degradation caused by edge spreading. The system includes an edge spread detector circuit that processes an input signal to detect variations in signal edges, which are indicative of spreading or distortion. The detector circuit generates an output that includes a sampling point, which represents a specific location or time within the detected edge spread. This sampling point can be used for further analysis, calibration, or correction of the signal. The system may also include a comparator circuit that compares the detected edge spread with a reference value to determine the extent of spreading. Additionally, a control circuit may adjust system parameters based on the detected edge spread to mitigate its effects. The system is particularly useful in applications where precise signal integrity is critical, such as high-speed communication systems, imaging sensors, or signal processing pipelines. By providing a measurable sampling point within the edge spread, the system enables more accurate characterization and compensation of signal distortions.
14. The device of claim 13 , wherein the sampling point is isolated from transitions in a data stream received by the data terminal.
A system for data transmission includes a data terminal that receives a data stream and a sampling circuit that captures data from the stream. The sampling circuit is configured to isolate a sampling point from transitions in the data stream, ensuring accurate data capture. The data terminal processes the received data stream, which may include digital or analog signals, and the sampling circuit operates to minimize errors caused by signal transitions. The isolation of the sampling point from these transitions prevents misalignment or corruption of the sampled data, improving reliability in data communication systems. The system may be used in high-speed data transmission applications where signal integrity is critical, such as in telecommunications, networking, or digital signal processing. The sampling circuit may employ techniques like phase-locked loops or delay-locked loops to synchronize sampling with the data stream while avoiding transition-induced noise. This design enhances data accuracy by ensuring that samples are taken at stable points in the signal, away from voltage or timing fluctuations that occur during transitions. The overall system improves signal fidelity and reduces error rates in data transmission.
15. The device of claim 9 , wherein the edge spread detector circuit comprises: an edge detector sub-circuit having an input coupled to the data terminal; and a shift register having an input coupled to an output of the edge detector sub-circuit.
This invention relates to electronic circuits for detecting signal edges, particularly in data transmission systems where accurate edge detection is critical for synchronization and signal integrity. The problem addressed is the need for reliable edge detection in high-speed data signals, where noise and signal distortion can lead to errors in determining edge positions. Traditional edge detection methods may suffer from latency or inaccuracies, impacting system performance. The invention describes a device with an edge spread detector circuit designed to improve edge detection accuracy. The circuit includes an edge detector sub-circuit connected to a data terminal, which processes incoming data signals to identify transitions or edges. The output of this sub-circuit is fed into a shift register, which captures and stores the detected edges over time. This allows the system to analyze edge patterns, detect spread or jitter, and improve synchronization. The shift register enables temporal analysis, helping to mitigate errors caused by noise or distortion. The combination of the edge detector and shift register provides a robust solution for high-speed data applications, ensuring precise edge detection and reducing synchronization errors. This approach enhances signal processing in communication systems, data storage devices, and other applications requiring accurate edge detection.
16. The device of claim 15 , wherein the shift register comprises a cyclic shift register.
A cyclic shift register is used in digital signal processing and data transmission systems to manage and manipulate data sequences. The problem addressed is the need for efficient, reversible data shifting operations in applications like error correction, encryption, and signal modulation, where data must be cyclically rotated without loss or distortion. A cyclic shift register is a specialized type of shift register that allows data to be shifted in a circular manner, meaning the last bit shifted out re-enters the register as the first bit. This enables continuous, looped data processing, which is critical for algorithms requiring repeated or reversible transformations. The register includes multiple storage elements (flip-flops or latches) connected in a closed loop, with control logic to handle the cyclic shifting. Input data is loaded into the register, and upon each clock cycle, the data is shifted one position, with the last bit wrapping around to the first position. This design ensures that data remains intact during shifting operations, making it suitable for applications like polynomial division in error detection, pseudorandom number generation, and digital filtering. The cyclic nature allows for efficient implementation of modular arithmetic and bitwise operations, reducing computational overhead in systems requiring frequent data rotation.
17. The device of claim 15 , wherein the edge detector sub-circuit comprises: a first flip flop having an input coupled to the data terminal; a second flip flop having an input coupled to an output of the first flip flop; a first logic gate having a first input coupled to the output of the first flip flop and having a second input coupled to an output of the second flip flop; and a second logic gate having a first input coupled to an output of the first logic gate and having a second input coupled to an output of the shift register.
The invention relates to digital signal processing, specifically edge detection in digital circuits. Edge detection is crucial for identifying transitions in digital signals, but traditional methods often require complex circuitry or consume excessive power. The invention addresses this by providing a compact and efficient edge detector sub-circuit for use in digital systems. The edge detector sub-circuit includes a first flip flop connected to a data terminal, capturing the input signal. A second flip flop is connected to the output of the first flip flop, introducing a delay to compare sequential signal states. A first logic gate, such as an XOR gate, is connected to the outputs of both flip flops to detect transitions by comparing current and previous signal states. A second logic gate, such as an AND gate, combines the output of the first logic gate with the output of a shift register to further refine edge detection. The shift register provides additional timing control, ensuring accurate edge detection while minimizing false triggers. This design reduces circuit complexity and power consumption while maintaining high detection accuracy. The sub-circuit is particularly useful in high-speed digital systems where efficient edge detection is critical.
18. The device of claim 17 , wherein the first logic gate comprises an XOR logic gate.
A device for processing digital signals includes a first logic gate and a second logic gate. The first logic gate receives a first input signal and a second input signal, and generates an output signal based on a logical operation between the two input signals. The second logic gate receives the output signal from the first logic gate and a third input signal, and generates a final output signal based on another logical operation. The first logic gate is specifically an XOR (exclusive OR) logic gate, which outputs a high signal when the first and second input signals are different and a low signal when they are the same. This configuration allows the device to perform conditional signal processing, such as parity checking, error detection, or data comparison, by leveraging the XOR gate's ability to detect mismatches between input signals. The second logic gate may perform additional logical operations, such as AND, OR, or another XOR, to further process the intermediate output before generating the final result. The device can be used in digital circuits, communication systems, or computing applications where signal comparison and conditional logic are required.
19. The device of claim 17 , wherein the second logic gate comprises an OR logic gate.
A device for digital signal processing includes a first logic gate and a second logic gate. The first logic gate receives a first input signal and a second input signal, and outputs a first logic result. The second logic gate receives the first logic result and a third input signal, and outputs a second logic result. The second logic gate is an OR logic gate, meaning it performs a logical OR operation on its inputs. The device may be part of a larger digital circuit, such as a microprocessor, a programmable logic device, or a custom integrated circuit, where such logic gates are used for signal conditioning, control logic, or data processing. The use of an OR gate in the second stage allows for flexible signal combination, enabling the device to implement functions like signal merging, conditional logic, or priority selection. This configuration improves signal processing efficiency by reducing the need for additional components while maintaining logical correctness. The device may also include additional logic gates or components to further process the output signal or interface with other digital systems.
20. A method for sampling data in an asynchronous communication interface system, comprising: oversampling an incoming data stream using a system clock frequency; identifying transitions in the incoming data stream; determining an edge spread for a data clock frequency of the incoming data stream, wherein the system clock frequency is a multiple of the data clock frequency; determining a sampling point based on the determined edge spread; adjusting a phase offset based on the determined sampling point; generating a clock signal having the data clock frequency and the adjusted phase offset; and sampling the incoming data stream using the data clock frequency based on the generated clock signal.
This invention relates to asynchronous communication interfaces, specifically addressing the challenge of accurately sampling data streams when the system clock and data clock operate at different frequencies. The method involves oversampling an incoming data stream using a system clock that operates at a higher frequency than the data clock. By oversampling, the system can precisely identify transitions in the data stream. The method then determines the edge spread of the data clock signal, which represents the variability in the timing of signal transitions. Using this edge spread, the system calculates an optimal sampling point to minimize errors. The phase offset of the data clock is adjusted accordingly to align the sampling point with the center of the data eye, ensuring reliable data capture. A clock signal is then generated with the adjusted phase offset and the data clock frequency, which is used to sample the incoming data stream. This approach improves synchronization in asynchronous communication systems, reducing bit errors and enhancing data integrity. The method is particularly useful in high-speed or variable-frequency communication environments where precise timing alignment is critical.
21. The method of claim 20 , wherein adjusting the phase offset based on the determined sampling point comprises adjusting the phase offset such that the generated clock signal has a rising edge at the sampling point.
A method for clock signal phase adjustment in data sampling systems addresses timing misalignment between a data signal and its corresponding clock signal, which can lead to sampling errors. The method involves determining an optimal sampling point on the data signal where the signal transitions between valid data states. The phase offset of the clock signal is then adjusted so that the rising edge of the clock signal aligns precisely with this sampling point. This ensures accurate data capture by synchronizing the clock's rising edge with the data signal's valid state transition. The adjustment process may involve measuring signal characteristics, such as voltage levels or transition timings, to identify the optimal sampling point. By dynamically aligning the clock's rising edge with the determined sampling point, the method improves data integrity and reduces errors in high-speed communication systems, digital signal processing, and other applications where precise timing is critical. The technique is particularly useful in scenarios where signal distortion or environmental factors cause timing variations.
22. The method of claim 20 , wherein determining the sampling point based on the determined edge spread comprises determining the sampling point is isolated from the determined edge spread.
A method for optimizing signal sampling in electronic systems addresses the challenge of accurately capturing signal transitions in the presence of edge spread, which can degrade signal integrity and measurement precision. Edge spread refers to the distortion or broadening of signal edges due to factors like noise, interference, or imperfect signal transmission. The method involves analyzing the signal to determine the extent of edge spread and then selecting a sampling point that is isolated from this spread. By ensuring the sampling point is sufficiently distant from the distorted edge region, the method improves the reliability of signal measurements, reducing errors caused by edge-related artifacts. This approach is particularly useful in high-speed digital systems, communication circuits, and signal processing applications where precise timing and accurate signal reconstruction are critical. The technique may be implemented in hardware, software, or a combination thereof, and can be applied to various types of signals, including digital, analog, or mixed-signal waveforms. The method enhances signal fidelity by mitigating the impact of edge spread, leading to more accurate data acquisition and processing.
23. The method of claim 22 , further comprising: verifying the sampling point is isolated from the determined edge spread; in response to the sampling point being isolated from the determined edge spread, sampling the incoming data stream at the data clock rate based on the generated clock signal; and in response to the sampling point not being isolated from the determined edge spread, determining a revised sampling point.
This invention relates to data sampling techniques in high-speed communication systems, particularly addressing challenges in accurately sampling incoming data streams affected by edge spread, which can degrade signal integrity and lead to errors. The method involves generating a clock signal synchronized with the incoming data stream and determining an initial sampling point for capturing data. A key aspect is analyzing the edge spread of the incoming signal to assess whether the sampling point is sufficiently isolated from this spread. If the sampling point is isolated, the data is sampled at the data clock rate using the generated clock signal. If not, the method adjusts the sampling point to ensure proper isolation from the edge spread before sampling. This iterative process improves sampling accuracy by dynamically adapting to signal variations, reducing errors caused by edge spread interference. The technique is particularly useful in high-speed data transmission systems where precise timing and signal integrity are critical.
24. The method of claim 23 , further comprising determining a revised edge spread for the data clock rate of the incoming data stream, wherein verifying the sampling point is isolated from the determined edge spread comprises verifying the sampling point is isolated from the revised edge spread.
This invention relates to data communication systems, specifically methods for optimizing sampling points in high-speed serial data transmission to improve signal integrity and reduce errors. The problem addressed is ensuring accurate data recovery by avoiding sampling points that are too close to signal transitions, which can lead to misinterpretation of data due to edge jitter or noise. The method involves analyzing an incoming data stream to determine an initial edge spread, which represents the range of possible transition points in the signal. A sampling point is then selected for extracting data from the stream, and the system verifies that this sampling point is sufficiently isolated from the edge spread to prevent interference from signal transitions. If the sampling point is not isolated, the method adjusts the sampling point or the data clock rate to ensure reliable data recovery. Additionally, the method may recalculate a revised edge spread based on the adjusted clock rate and reverify the sampling point's isolation from this revised edge spread. This iterative process ensures that the sampling point remains stable and accurate, even under varying signal conditions. The technique is particularly useful in high-speed serial interfaces where precise timing is critical for maintaining data integrity.
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December 8, 2020
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