Virtualized Synchronous Ethernet interfaces

1. A Virtualized Synchronous Ethernet method comprising: in a network element supporting a plurality of separate slices over a common Ethernet physical (PHY) connection, each separate slice allowing traffic for a respective application, determining a common PHY frequency that is shared by each of the plurality of separate slices; for a specific slice of the plurality of separate slices, obtaining a bit-level accurate count (C n ) for the specific slice over an accumulation window from a second network element for synchronization therewith via one of Ethernet Synchronization Messaging Channel (ESMC) packets, dedicated Ethernet packets, Flexible Ethernet (FlexE) overhead, and Continuity Check Messages (CCMs); and determining a client clock for the specific slice based on the common PHY frequency and the bit-level accurate count (C n ).

2. The Virtualized Synchronous Ethernet method of claim 1 , wherein the obtaining of the bit-level accurate count (C n ) is via appending a Type-Length-Value (TLV).

3. The Virtualized Synchronous Ethernet method of claim 1 , further comprising protecting the obtaining of the bit-level accurate count (C n ) from the second network element via one or more of repeating transmission, utilizing an incrementing field, and utilizing an acknowledgment scheme.

4. The Virtualized Synchronous Ethernet method of claim 1 , wherein the bit-level accurate count (C n ) over the accumulation window is obtained utilizing accumulators and the determining the client clock is via Digital Phase Lock Loops (DPLLs).

5. The Virtualized Synchronous Ethernet method of claim 4 , wherein the accumulation window has a value based on one or more of a bandwidth of the DPLLs and a sampling rate of the accumulators.

6. A Virtualized Synchronous Ethernet system comprising: circuitry configured to receive a common Ethernet physical (PHY) connection which includes a plurality of separate slices, each separate slice allowing traffic for a respective application; circuitry configured to determine a common PHY frequency that is shared by each of the plurality of separate slices; circuitry configured to obtain, for a specific slice of the plurality of separate slices, a bit-level accurate count (C n ) over an accumulation window, wherein the bit-level accurate count (C n ) is obtained from a second network element for synchronization therewith via one of the Ethernet Synchronization Messaging Channel (ESMC) packets, dedicated Ethernet packets, Flexible Ethernet (FlexE) overhead, and Continuity Cheek Messages (CCMs); and circuitry configured to determine a client clock for the specific slice based on the common PHY frequency and the bit-level accurate count (C n ).

7. The Virtualized Synchronous Ethernet system of claim 6 , wherein the bit-level accurate count is obtained via an appended Type-Length-Value (TLV).

8. The Virtualized Synchronous Ethernet system of claim 6 , further comprising circuitry configured to protect reception of the bit-level accurate count (C n ) from the second network element via one or more of repeating transmission, utilizing an incrementing field, and utilizing an acknowledgment scheme.

9. The Virtualized Synchronous Ethernet system of claim 6 , wherein the bit-level accurate count (C n ) over the accumulation window is obtained utilizing accumulators and the client clock is determined utilizing Digital Phase Lock Loops (DPLLs).

10. A network element comprising: one or more ports configured to receive a common Ethernet physical (PHY) connection which includes a plurality of separate slices, each separate slice allowing traffic for a respective application; a switching fabric interconnecting the one or more ports; and a controller configured to determine a common PHY frequency that is shared by each of the plurality of separate slices, obtain, for a specific slice of the plurality of separate slices, a bit-level accurate count (C n ) over an accumulation window, wherein the bit-level accurate count (C n ) is obtained from a second network element for synchronization therewith via one of Ethernet Synchronization Messaging Channel (ESMC) packets, dedicated Ethernet packets, Flexible Ethernet (FlexE) overhead, and Continuity Check Messages (CCMs), and determine a client clock for the specific slice based on the common PHY frequency and the bit-level accurate count (C n ).

11. The network element of claim 10 , wherein the bit-level accurate count (C n ) is obtained via an appended Type-Length-Value (TLV).

12. The network element of claim 10 , wherein the bit-level accurate count (C n ) over the accumulation window is obtained utilizing accumulators and the client clock is determined utilizing Digital Phase Lock Loops (DPLLs).