Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A circuit for implementing single event upset (SEU) parity detection comprising: an SEU parity detection circuit detecting unwanted state changes due to SEUs in a latch having a default state of zero; the latch including an L1 latch and an L2 latch with the L2 latch having the connected output and being used and monitored for a flip due to SEU; a pair of series-connected field effect transistors (FETs) connected between a drive input of a parity control circuit and ground potential and having a respective gate input applied by the L1 latch and the L2 latch; and an L2 clock applied to the L2 latch and the parity control circuit.
This invention relates to integrated circuit design and addresses the problem of detecting single event upsets (SEUs), which are transient errors caused by radiation that can flip the state of memory elements like latches. The described circuit implements SEU parity detection. It includes a latch designed to detect unwanted state changes caused by SEUs. This latch has a default state of zero. The latch itself is composed of two sub-latches: an L1 latch and an L2 latch. The output of the L2 latch is the primary output of the overall latch and is monitored for flips caused by SEUs. The circuit also features a parity control circuit. Connected between a drive input of this parity control circuit and ground are two field-effect transistors (FETs) connected in series. The gate inputs of these two FETs are controlled by the states of the L1 latch and the L2 latch, respectively. An L2 clock signal is applied to both the L2 latch and the parity control circuit. This clocking mechanism is crucial for synchronizing the detection and control operations. The arrangement of the FETs and their control by the latches allows for the detection of parity changes indicative of an SEU.
2. The circuit as recited in claim 1 , wherein said pair of series-connected field effect transistors (FETs) detect unwanted state changes.
A circuit includes a pair of series-connected field effect transistors (FETs) configured to detect unwanted state changes in an electronic system. The FETs are arranged such that their gate terminals are connected to a common input, while their drain terminals are connected to a common output. The source terminals of the FETs are connected to separate voltage references or ground, creating a differential configuration. This arrangement allows the circuit to monitor for unintended voltage fluctuations or signal transitions that could indicate faults, interference, or unauthorized access. The FETs operate in a manner that amplifies or isolates these unwanted state changes, enabling detection and mitigation. The circuit may be integrated into larger systems, such as microcontrollers, memory devices, or communication interfaces, to enhance reliability and security by identifying and responding to abnormal conditions. The detection mechanism relies on the inherent properties of FETs, such as threshold voltage and channel resistance, to distinguish between normal and anomalous states. The circuit may also include additional components, such as comparators or logic gates, to process the detected signals and trigger corrective actions. This design improves system robustness by providing early warning of potential failures or security breaches.
3. The circuit as recited in claim 1 , wherein said pair of series-connected field effect transistors (FETs) are N-channel NFETs.
This invention relates to a circuit design involving a pair of series-connected field effect transistors (FETs) configured as N-channel NFETs. The circuit is designed to address challenges in power management, signal switching, or voltage regulation, where precise control of current flow and switching characteristics is critical. The use of N-channel NFETs in a series configuration allows for efficient current conduction and switching, leveraging the inherent properties of NFETs, such as lower on-resistance and faster switching speeds compared to other transistor types. The series connection of the NFETs enables enhanced control over voltage levels and current flow, which is particularly useful in applications requiring high-speed switching or precise voltage regulation. The circuit may be part of a larger system, such as a power converter, a signal modulator, or a voltage regulator, where the series-connected NFETs contribute to improved performance, efficiency, or reliability. The design ensures that the NFETs operate within their optimal voltage and current ranges, minimizing power loss and heat generation while maintaining stable operation under varying load conditions. This configuration is particularly advantageous in integrated circuits (ICs) and power electronics, where compact, efficient, and reliable switching solutions are essential.
4. The circuit as recited in claim 3 , wherein the parity control circuit includes a P-channel PFET-based parity control latch circuit.
A circuit for error detection in digital systems includes a parity control circuit that generates and checks parity bits to identify errors in data transmission or storage. The parity control circuit is designed to operate efficiently within integrated circuits, ensuring reliable data integrity. In this specific implementation, the parity control circuit incorporates a P-channel field-effect transistor (PFET)-based parity control latch circuit. This latch circuit uses PFETs to store and manage parity bits, providing a stable and low-power solution for parity operations. The PFET-based design enhances performance by reducing power consumption and improving switching speed compared to traditional implementations. The circuit is particularly useful in applications requiring high-speed data processing with minimal error rates, such as memory systems, communication protocols, and digital signal processing. The PFET-based latch ensures robust parity generation and checking, contributing to overall system reliability.
5. The circuit as recited in claim 4 , wherein the P-channel PFET-based parity control latch circuit includes a P-channel PFET-based parity latch circuit.
A circuit for parity control in digital systems addresses the need for efficient and reliable parity generation and checking in integrated circuits. The circuit includes a P-channel PFET-based parity control latch circuit, which further comprises a P-channel PFET-based parity latch circuit. This latch circuit is designed to generate or verify parity bits in digital data streams, ensuring data integrity during transmission or storage. The use of P-channel PFETs (P-type Field-Effect Transistors) in the latch circuit provides advantages such as reduced power consumption and improved noise immunity compared to traditional N-channel implementations. The parity control latch circuit operates by evaluating input data bits and producing a parity output that indicates whether the number of logical '1's in the input data is even or odd, depending on the desired parity scheme (even or odd parity). The circuit may be integrated into larger digital systems, such as memory controllers, communication interfaces, or error detection modules, to enhance data reliability. The P-channel PFET-based design ensures robust performance under varying operating conditions while maintaining low power consumption, making it suitable for modern low-power and high-performance applications.
6. The circuit as recited in claim 4 , includes an inverted output of the L1 latch and a true output of the L2 latch applied to a respective gate of the said pair of series-connected NFETs.
This invention relates to integrated circuit design, specifically a latch-based circuit configuration for controlling a pair of series-connected NFETs (n-channel field-effect transistors). The problem addressed is the need for efficient and reliable switching control in digital or mixed-signal circuits, particularly where precise timing and signal integrity are critical. The circuit includes a first latch (L1) and a second latch (L2), each generating complementary outputs. The inverted output of L1 and the true output of L2 are applied to the gates of the two NFETs, which are connected in series. This configuration ensures that the NFETs are driven in a coordinated manner, preventing simultaneous conduction that could cause unwanted current paths or signal degradation. The latches provide stable, synchronized control signals, improving the circuit's robustness against noise and timing variations. The NFETs are arranged such that their source-drain paths are connected in series, with the gate of the first NFET receiving the inverted output from L1 and the gate of the second NFET receiving the true output from L2. This setup ensures that the NFETs operate in a complementary fashion, enhancing switching efficiency and reducing power dissipation. The circuit is particularly useful in applications requiring precise timing control, such as clock distribution networks, data synchronization, or power management systems. The use of latches ensures that the control signals are stable and free from glitches, improving overall system reliability.
7. The circuit as recited in claim 5 , includes a plurality of L1 L2 latches connected in a chain, each including said pair of series-connected field effect transistors (FETs).
The invention relates to a digital circuit design for high-speed data processing, specifically addressing the challenge of minimizing propagation delay and power consumption in latch-based circuits. The circuit comprises a chain of L1 and L2 latches, each containing a pair of series-connected field-effect transistors (FETs). The L1 and L2 latches are configured to sequentially capture and transfer data signals, ensuring synchronized data propagation through the chain. The series-connected FETs within each latch act as a switching mechanism to control data flow, reducing signal contention and improving timing performance. The chain structure allows for pipelined data processing, where each latch stage operates in a staggered manner to maintain data integrity and minimize latency. This design is particularly useful in high-frequency applications where low-power, high-speed data transfer is critical, such as in microprocessors, digital signal processors, or memory interfaces. The use of series-connected FETs in each latch stage optimizes the trade-off between speed and power efficiency, making the circuit suitable for advanced semiconductor technologies.
8. The circuit as recited in claim 7 , includes a L2 clock parity circuit trigger shared across each of the plurality of L1 L2 latches.
A circuit for detecting and correcting errors in a multi-level latch system, particularly in integrated circuits with hierarchical latch structures such as L1 and L2 latches. The circuit addresses the challenge of maintaining data integrity in high-speed digital systems where transient faults or noise can corrupt stored data. The invention includes a shared L2 clock parity circuit trigger that monitors the parity of data stored in multiple L2 latches, which are themselves connected to L1 latches. The L2 clock parity circuit trigger generates a signal when a parity error is detected, indicating potential data corruption. This shared trigger mechanism reduces hardware complexity by centralizing parity checks across multiple latches rather than requiring individual parity circuits for each latch. The circuit may also include error correction logic that uses the parity signal to identify and correct errors, ensuring reliable operation. The design is particularly useful in systems requiring high fault tolerance, such as processors, memory controllers, or other digital logic circuits where data integrity is critical. The shared parity trigger optimizes power efficiency and reduces circuit area by minimizing redundant components while maintaining robust error detection capabilities.
9. The circuit as recited in claim 7 , includes an L1 Data and Scan clock are shared across each of the plurality of L1 L2 latches.
A circuit design for integrated circuits includes a shared clock distribution system for latching data and scan operations. The circuit comprises multiple latches organized into at least two hierarchical levels, such as L1 and L2 latches, where the L1 latches are positioned closer to the processing core and the L2 latches are positioned further away. The circuit includes a clock distribution network that provides a single clock signal, referred to as the L1 Data and Scan clock, which is shared across all L1 and L2 latches. This shared clock signal is used for both data processing and scan testing operations, eliminating the need for separate clock signals for each function. The shared clock approach reduces circuit complexity, minimizes power consumption, and simplifies timing management by synchronizing all latches with a unified clock. The design ensures that data and scan operations are performed in a coordinated manner, improving overall system reliability and testability. The circuit may be implemented in various integrated circuit architectures, including microprocessors, application-specific integrated circuits (ASICs), and field-programmable gate arrays (FPGAs).
10. The circuit as recited in claim 7 , includes L2 latch flip from a SEU relative to the L1 state detected by the resultant bias state of the group of said pair of series-connected NFETs and compared to an initial parity input.
A circuit is designed to detect and mitigate single-event upset (SEU) errors in latch-based systems. The circuit includes a pair of series-connected NFETs (n-type field-effect transistors) that generate a bias state indicative of the latch state. This bias state is compared to an initial parity input to determine whether an SEU has caused an unintended flip in the latch state. If an SEU is detected, the circuit triggers a correction mechanism to restore the latch to its original state. The NFET pair acts as a sensing element, where their combined electrical behavior reflects the latch state, allowing for real-time error detection. The initial parity input serves as a reference to validate the current state, ensuring data integrity. This approach enhances reliability in digital systems by autonomously detecting and correcting SEU-induced errors without external intervention. The circuit is particularly useful in radiation-prone environments, such as aerospace or high-energy physics applications, where latch flips due to SEUs can lead to system failures. The NFET-based sensing mechanism provides a low-power, high-speed solution for error detection, while the parity comparison ensures accurate state validation. The overall design improves fault tolerance in digital circuits by combining hardware-based error detection with automatic correction.
11. The circuit as recited in claim 10 , includes a mis-compare indicating parity failure driven through to parity out of said P-channel PFET-based parity control circuit.
A circuit for detecting and signaling parity errors in digital systems, particularly in memory or data processing applications, includes a P-channel field-effect transistor (PFET)-based parity control circuit. The circuit monitors data for parity mismatches, where a parity bit does not match the expected value, indicating a data error. When a mis-compare occurs, the circuit generates a parity failure signal. This signal is driven through the PFET-based control circuit to an output pin or register, providing a clear indication of the parity error. The PFET-based design ensures efficient signal propagation and low power consumption while maintaining reliability in error detection. The circuit may be integrated into larger systems, such as memory controllers or error-checking logic, to enhance data integrity. The parity failure signal can trigger corrective actions, such as data retransmission or error logging, depending on the system's requirements. The design optimizes speed and accuracy in parity error detection, addressing the need for robust error-checking mechanisms in high-speed digital circuits.
12. The circuit as recited in claim 10 , includes a mis-compare indicating parity failure at a parity output of said P-channel PFET-based parity control latch circuit.
A circuit includes a P-channel PFET-based parity control latch circuit that generates a parity output. The circuit detects a mis-compare condition, indicating a parity failure, at this parity output. The parity control latch circuit is designed to evaluate parity bits and generate a signal indicating whether the parity is correct or incorrect. When the parity is incorrect, the circuit identifies this as a mis-compare event, signaling a parity failure. This failure detection mechanism ensures data integrity by flagging errors in parity checks, which are commonly used in digital systems to verify the correctness of transmitted or stored data. The circuit may be part of a larger system, such as a memory controller, error detection module, or data processing unit, where reliable parity verification is critical. The use of a PFET-based latch ensures low-power operation while maintaining fast response times for error detection. The circuit's ability to quickly identify parity failures helps prevent data corruption and improves system reliability in applications where error detection is essential.
13. A design structure embodied in a machine readable medium used in a design process, the design structure comprising: a circuit tangibly embodied in the machine readable medium used in the design process, said circuit for implementing single event upset (SEU) parity detection, said a SEU parity detection circuit detecting unwanted state changes due to SEUs in a latch having a default state of zero; said SEU parity detection circuit comprising: the latch including an L1 latch and an L2 latch with the L2 latch having the connected output and being used and monitored for a flip due to SEU; a pair of series-connected field effect transistors (FETs) connected between a drive input of a parity control circuit and ground potential and having a respective gate input applied by the L1 latch and the L2 latch; and an L2 clock applied to the L2 latch and the parity control circuit; wherein the design structure, when read and used in the manufacture of a semiconductor chip produces a chip comprising said SEU parity detection circuit.
This invention relates to semiconductor circuit design for detecting single event upset (SEU) errors in digital circuits, particularly in latches that default to a zero state. SEUs are transient faults caused by radiation or other disturbances, leading to unintended state changes in memory elements. The invention addresses the need for reliable SEU detection in latches to ensure data integrity in semiconductor chips, especially in critical applications like aerospace, automotive, and medical devices. The design structure includes a SEU parity detection circuit implemented in a machine-readable medium for semiconductor manufacturing. The circuit monitors a latch composed of two sub-latches (L1 and L2), where L2 is the primary latch being monitored for SEU-induced state flips. A pair of series-connected field-effect transistors (FETs) connects the drive input of a parity control circuit to ground, with their gates controlled by the outputs of L1 and L2. An L2 clock signal synchronizes the L2 latch and the parity control circuit. When an SEU causes an unintended state change in L2, the FETs and parity control circuit detect the anomaly, enabling error correction or mitigation. The design structure, when used in semiconductor fabrication, produces a chip with integrated SEU detection capabilities, enhancing reliability in radiation-prone environments.
14. The design structure of claim 13 , wherein the design structure comprises a netlist, which describes said SEU parity detection circuit.
The invention relates to error detection in integrated circuits, specifically addressing single-event upset (SEU) errors caused by radiation or other transient faults. SEU errors can corrupt data in memory or logic circuits, leading to system failures. The invention provides a design structure for an SEU parity detection circuit that identifies and mitigates such errors. The design structure includes a netlist, which is a detailed description of the circuit's components and their interconnections, defining the SEU parity detection circuit's functionality. The netlist specifies how the circuit monitors data for parity errors, allowing it to detect and correct SEU-induced faults. The circuit may include parity generation and checking logic, error correction mechanisms, and interfaces to memory or logic blocks. The design structure ensures that the SEU parity detection circuit can be synthesized, verified, and fabricated into a physical integrated circuit. The invention improves system reliability by providing a robust method for detecting and correcting SEU errors in digital circuits.
15. The design structure of claim 13 , wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.
16. The design structure of claim 13 , wherein the design structure includes at least one of test data files, characterization data, verification data, or design specifications.
17. The design structure of claim 13 , wherein said SEU parity detection circuit includes a plurality of L1 L2 latches connected in a chain, each including said pair of series-connected field effect transistors (FETs).
The invention relates to error detection in integrated circuits, specifically addressing single-event upset (SEU) vulnerabilities in semiconductor devices. SEU occurs when ionizing radiation disrupts circuit operation, causing data corruption. The invention provides a design structure for an SEU parity detection circuit that enhances fault tolerance in digital systems. The circuit includes a chain of L1 and L2 latches, each containing a pair of series-connected field-effect transistors (FETs). These latches are arranged sequentially to monitor data integrity. The series-connected FETs in each latch form a differential pair, enabling robust parity detection by comparing complementary signals. When an SEU event occurs, the differential configuration helps detect mismatches, allowing the system to identify and correct errors. The design structure ensures that the parity detection circuit operates reliably under radiation exposure, reducing the risk of undetected data corruption. The chain of latches provides a scalable solution, allowing integration into various digital circuits where SEU resilience is critical, such as aerospace, automotive, and high-reliability computing applications. The use of FET-based latches ensures low power consumption while maintaining high detection accuracy. This approach improves system reliability without significantly increasing circuit complexity or area overhead.
18. The design structure of claim 17 , wherein said SEU parity detection circuit includes a L2 clock parity circuit trigger shared across each of the plurality of L1 L2 latches.
The invention relates to error detection in integrated circuits, specifically addressing single-event upset (SEU) errors in latch-based designs. SEU errors occur when ionizing radiation disrupts circuit operation, causing data corruption in memory elements like latches. The invention improves SEU detection by implementing a shared parity detection mechanism across multiple latches to enhance reliability and reduce hardware overhead. The design includes a parity detection circuit that monitors a plurality of L1 and L2 latches, which are used to store and propagate data in a pipelined or multi-stage system. The parity detection circuit detects errors by checking the parity (even or odd count) of data bits stored in these latches. A key feature is the inclusion of a shared L2 clock parity circuit trigger, which synchronizes parity checks across all L1 and L2 latches. This shared trigger ensures that parity checks are performed in a coordinated manner, reducing the likelihood of undetected errors due to timing mismatches. By sharing the parity detection logic and clock trigger across multiple latches, the design minimizes redundant circuitry, conserving chip area and power while maintaining robust error detection. The shared trigger also simplifies the implementation of parity checks, making the system more scalable for designs with many latches. This approach is particularly useful in high-reliability applications, such as aerospace, automotive, and medical devices, where radiation-induced errors must be detected and mitigated.
19. A method for implementing single event upset (SEU) parity detection comprising: providing a single event upset (SEU) parity detection circuit for detecting unwanted state changes due to SEUs in a latch having a default state of zero; providing the latch including an L1 latch and an L2 latch with the L2 latch having the connected output and being used and monitored for a flip due to SEU; providing a pair of series-connected field effect transistors (FETs) connected between a drive input of a parity control circuit and ground potential and having a respective gate input applied by the L1 latch and the L2 latch; applying an L2 clock to the L2 latch and the parity control circuit.
20. The method of claim 19 , wherein said pair of series-connected field effect transistors (FETs) are N-channel NFETs and the parity control circuit includes a P-channel PFET-based parity control circuit.
The invention relates to a method for implementing a parity control circuit in a semiconductor device, specifically addressing the need for efficient and reliable parity generation and checking in digital systems. The method involves using a pair of series-connected N-channel field-effect transistors (NFETs) to generate or check parity bits, where the NFETs are configured to operate in a complementary manner to ensure accurate parity determination. The parity control circuit further includes a P-channel FET (PFET)-based parity control circuit, which works in conjunction with the NFETs to enhance the overall performance and reliability of the parity operation. The PFET-based circuit provides complementary functionality, ensuring that the parity logic can handle both even and odd parity configurations. The method optimizes the transistor configuration to minimize power consumption and improve speed, making it suitable for high-performance digital systems where error detection and correction are critical. The use of NFETs and PFETs in a balanced configuration ensures robust parity operations while maintaining low latency and high efficiency.
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January 19, 2021
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