Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A computer-implemented method for assessing the trustworthiness of a particular microelectronics device design representation, including determining correct capture and translation of design intent with regards to expected operation of the particular microelectronics device design representation, without exposing proprietary details of the particular microelectronics device design representation or proprietary details of a Bitstream data format corresponding to the particular microelectronics device design representation, comprising: receiving, in a computing device, Placelist information and Bitstream data that corresponds to the particular microelectronics device design representation; generating, using the computing device, a set of Placelist expectations corresponding to the received Placelist information and a set of Bitstream expectations corresponding to the received Bitstream data, each expectation providing a descriptive representation of an individual physical or logical resource and its associated geographical region on a semiconductor chip; comparing, using the computing device, each Placelist expectation with each Bitstream expectation to identify matching expectations for which a corresponding Placelist expectation or Bitstream expectation is found and unmatched expectations for which a corresponding Placelist expectation or Bitstream expectation is not found; and generating output information, using the computing device, which provides an indication of the trustworthiness of the particular microelectronics device design representation based upon a result of comparing the Placelist expectations with the Bitstream expectations, wherein the indication of the trustworthiness includes a determination of whether a design intent with regards to expected operation of the particular microelectronics device design representation is correctly captured and translated, and wherein the generated output information includes information for verifying or validating the particular microelectronics device design representation based upon a result of comparing Placelist expectations with Bitstream expectations.
2. The method of claim 1 , wherein the Placelist expectations and/or the Bitstream expectations are generated as encoded or encrypted data structures or as data structures having a predetermined undisclosed proprietary bit format.
3. The method of claim 1 , wherein the received Bitstream data is encrypted or encoded and the computing device performs decryption or decoding of the Bitstream data prior to generating Bitstream expectations.
4. The method of claim 1 , further including using the computing device to generate a set of unmet expectations comprising one or more unmatched Placelist or Bitstream expectation for which a corresponding Placelist expectation or Bitstream expectation is not found.
5. The method of claim 4 , wherein the computing device performs a process of filtering the set of unmet expectations using one or more predetermined selective information filters/techniques.
6. The method of claim 5 , wherein one or more of the selective information filters/techniques are based upon a predetermined set of trust attribute rules or heuristic methods.
This invention relates to information filtering systems designed to improve the accuracy and relevance of data retrieval in digital environments. The core problem addressed is the challenge of efficiently filtering and selecting information from large datasets while ensuring the results meet specific trustworthiness criteria. Traditional filtering methods often rely on basic keyword matching or user preferences, which may not account for the reliability or credibility of the information sources. The invention introduces a method that enhances information filtering by incorporating a predetermined set of trust attribute rules or heuristic methods. These rules define criteria for evaluating the trustworthiness of data sources, such as the reputation of the source, the recency of the information, or the consistency of the data with known facts. Heuristic methods may involve statistical analysis, pattern recognition, or machine learning techniques to dynamically assess the reliability of information in real-time. By applying these trust-based filters, the system can prioritize or exclude information based on its credibility, improving the overall quality of the filtered results. The method can be applied in various domains, including search engines, social media platforms, or enterprise data management systems, where ensuring the trustworthiness of information is critical. The use of predefined rules or adaptive heuristics allows the system to adapt to different contexts and user needs, providing more accurate and reliable information retrieval. This approach reduces the risk of misinformation while enhancing user trust in the filtered results.
7. The method of claim 1 , wherein the indication in the output information is based upon one or more unmatched Placelist expectation or Bitstream expectation for which a corresponding Placelist expectation or Bitstream expectation is not found.
8. The method of claim 1 , wherein the computing device is a mobile computing device or is contained in an information processing system, apparatus or network of computers and the generating of Placelist expectations and Bitstream expectations is implemented via an executable software application or utility stored or resident on the mobile computing device, information processing system, apparatus or network of computers.
9. The method of claim 1 , wherein, in addition to generating a set of Placelist expectations, the computing device generates a characterization file containing characterization information regarding the received Placelist information, wherein the characterization file is generated by the computing device using an encryption or one-way encoding process that precludes translation of the characterization information into a functional netlist.
10. The method of claim 1 , wherein the computing device receives a characterization file, the received characterization file containing netlist characterization information that corresponds to the particular microelectronics device design representation, and wherein the received characterization file is used by the computing device for comparing with generated Bitstream expectations.
11. A method, executed using an information processing apparatus having one or more processors, for assessing the trustworthiness of a microelectronics device design representation, including determining correct capture and translation of design intent with regards to expected operation of the microelectronics device design representation, without exposing proprietary details of the design or proprietary details of a binary data structure format used for a bit stream that corresponds to the microelectronics device design representation, comprising: receiving in the information processing apparatus placed-and-routed netlist information which corresponds to the design and a bit stream of microelectronic device configuration data which corresponds to the design; generating, using one or more processors of the information processing apparatus, a first set of expectations corresponding to the received placed-and-routed netlist information and a second set of expectations corresponding to the received bit stream microelectronic device configuration data, each generated expectation comprising a description representative of an individual physical or logical resource and its associated geographical region of the microelectronics device; comparing, using one or more processors of the information processing apparatus, each expectation of the first set of expectations with each expectation of the second set of expectations to identify matching expectations for which a corresponding first expectation or second expectation is found and unmatched expectations for which a corresponding first expectation or second expectation is not found; and generating a report, using the information processing apparatus, wherein the report contains information indicative of the trustworthiness of the microelectronics device design representation based upon a result of comparing the first set of expectations with the second set of expectations, wherein the indication of the trustworthiness includes a determination of whether the design intent with regards to expected operation of the particular microelectronics device design representation is correctly captured and translated, wherein the information includes information for verifying or validating the microelectronics device design representation based upon a result of comparing the first set of expectations with the second set of expectations.
12. The method of claim 11 , wherein the generating of first and/or second sets of expectations includes encoding or encrypting the sets of expectations or producing the sets of expectations in a predetermined undisclosed proprietary data structure format.
13. The method of claim 11 , wherein the information processing apparatus is a mobile computing device or other information processing system, apparatus or network and the generating of a set of first expectations or set of second expectations is implemented via an executable software application or utility stored on the mobile computing device or other information processing system, apparatus or network.
This invention relates to information processing systems, particularly mobile computing devices or other information processing systems, apparatus, or networks, that generate expectations for data processing tasks. The problem addressed is the need for efficient and accurate expectation generation in dynamic computing environments, such as mobile devices, where processing resources and data availability may vary. The invention involves an information processing apparatus, such as a mobile computing device, that generates a set of first expectations or a set of second expectations. These expectations are derived from executable software applications or utilities stored on the device or within the system. The expectations may relate to data processing outcomes, system behavior, or user interactions, enabling the system to anticipate and optimize performance. The method ensures that the generated expectations are contextually relevant and adaptable to the device's current state, improving efficiency and user experience. The system may also include mechanisms to refine or update these expectations based on real-time data or user feedback, ensuring continuous improvement in accuracy. By leveraging software applications or utilities, the invention provides a flexible and scalable solution for expectation generation across various computing environments. This approach enhances decision-making processes, reduces processing overhead, and improves overall system responsiveness.
14. A non-transitory computer-readable storage medium on which are stored computer readable instructions which, when executed by a computer processor, cause the processor to perform operations for assessing the trustworthiness of a particular microelectronics device design representation, including determining correct capture and translation of design intent with regards to expected operation of the particular microelectronics device design representation, without exposing proprietary details of the particular microelectronics device design representation or proprietary details of an associated Bitstream binary data structure format, said operations comprising: receiving Placelist information and Bitstream data that correspond to the design of the microelectronics device; generating a set of Placelist expectations corresponding to the received Placelist information and a set of Bitstream expectations corresponding to the received Bitstream data, each expectation comprising a description representative of an individual physical or logical resource and its associated geographical region of the microelectronics device; comparing each Placelist expectation with each Bitstream expectation in respective sets to identify matching expectations for which a corresponding Placelist expectation or Bitstream expectation is found and unmatched expectations for which a corresponding Placelist expectation or Bitstream expectation is not found; and generating a report based upon a result of comparing Placelist expectations with Bitstream expectations, wherein the report contains information indicative of the trustworthiness of the particular microelectronics device design representation, wherein the indication of the trustworthiness includes a determination of whether the design intent with regards to expected operation of the particular microelectronics device design representation is correctly captured and translated, wherein the report includes information for verifying or validating the particular microelectronics device design representation based upon a result of comparing Placelist expectations with Bitstream expectations.
The field of microelectronics design involves creating complex integrated circuits, where design intent must be accurately captured and translated into physical implementations. A critical challenge is verifying the trustworthiness of a microelectronics device design representation without exposing proprietary details of the design or its associated Bitstream binary data structure format. This verification ensures that the design operates as intended while protecting intellectual property. A solution involves a computer-implemented method for assessing design trustworthiness by analyzing Placelist information and Bitstream data corresponding to the microelectronics device. The method generates Placelist expectations and Bitstream expectations, each describing individual physical or logical resources and their geographical regions within the device. These expectations are compared to identify matches and mismatches, indicating whether the design intent is correctly captured and translated. A report is generated, providing trustworthiness information and validation data based on the comparison results. The report helps verify the design without revealing proprietary details, ensuring both correctness and security in the design process. This approach is particularly useful in environments where intellectual property protection is critical, such as in semiconductor manufacturing and design verification.
15. The non-transitory computer-readable storage medium of claim 14 , wherein the generated Placelist expectations and/or the generated Bitstream expectations are generated as encoded or encrypted data structures or as data structures having a predetermined undisclosed proprietary bit format.
16. A information processing utility/tool including processor executable instructions which, when executed by a processor, causes the processor to perform operations for assessing the trustworthiness of a particular FPGA design representation, including determining correct capture and translation of design intent with regards to expected operation of the particular FPGA design representation, without exposing proprietary details of the particular FPGA design representation or proprietary details of an associated Bitstream binary data structure format, said operations comprising: receiving, by a computer input device in communication with the processor, an input including Placelist information and binary Bitstream data that correspond to the FPGA design; generating, by the processor, a set of Placelist expectations corresponding to the received Placelist information and a set of Bitstream expectations corresponding to the received Bitstream data, each expectation representative of an individual physical or logical resource and its associated geographical location on a semiconductor device, wherein the Placelist expectations and/or the Bitstream expectations are generated as encoded or encrypted data structures or as data structures having a predetermined undisclosed proprietary format; comparing, by the processor, Placelist expectations with Bitstream expectations to identify matching expectations for which a corresponding Placelist expectation or Bitstream expectation is found and unmatched expectations for which a corresponding Placelist expectation or Bitstream expectation is not found; and generating, by the processor, an output which is indicative of the trustworthiness of the particular FPGA design representation that is based upon a result of comparing Placelist expectations with Bitstream expectations, wherein the indication of the trustworthiness includes a determination of whether the design intent with regards to expected operation of the particular FPGA device design representation is correctly captured and translated, wherein the generated output includes information for verifying or validating the particular FPGA design representation based upon a result of comparing Placelist expectations with Bitstream expectations.
17. The information processing utility/tool of claim 16 , wherein the processor and computer readable instructions are instantiated on a same semiconductor device.
18. The information processing utility/tool of claim 16 , wherein the instructions are implemented as an executable software application stored on a mobile computing device or other information processing system, apparatus or network.
19. A system for assessing the trustworthiness of an FPGA design representation, including determining correct capture and translation of design intent with regards to expected operation of the FPGA design representation, without exposing proprietary details of the FPGA design representation or proprietary details of an associated Bitstream binary data structure format, comprising: a computer input device configured to receive Placelist information and binary Bitstream data, wherein the Placelist information comprises a structural netlist of logic element primitives and associated electrical connections for the FPGA and the Bitstream data is binary data representative of a configuration of physical semiconductor resources for the FPGA; a storage device configured to store an information database of generated Placelist expectations and generated Bitstream expectations of the FPGA design representation, each generated expectation being representative of an individual physical or logical resource and its associated geographical location on the FPGA device; and a processor in communication with the storage device and the computer input device, wherein the processor is configured to: generate a set of Placelist expectations corresponding to the received Placelist information and a set of Bitstream expectations corresponding to the received Bitstream data, wherein the Placelist expectations and/or the Bitstream expectations are generated as encoded or encrypted data structures or as data structures having a predetermined undisclosed proprietary format, store the generated sets of Placelist expectations and Bitstream expectations into the information database, compare Placelist expectations and Bitstream expectations stored in the information database to identify matching expectations for which a corresponding Placelist expectation or Bitstream expectation is found and unmatched expectations for which a corresponding Placelist expectation or Bitstream expectation is not found, and generate an output, based upon a result of comparing Placelist expectations with Bitstream expectations, indicative of the trustworthiness of the particular FPGA design representation, wherein the indication of the trustworthiness includes a determination of whether the design intent with regards to expected operation of the FPGA design representation is correctly captured and translated, wherein the generated output includes information for verifying or validating the FPGA design representation based upon a result of comparing Placelist expectations with Bitstream expectations.
The system assesses the trustworthiness of an FPGA design representation by verifying the correct capture and translation of design intent without exposing proprietary details of the design or Bitstream binary data structure. The system receives Placelist information, which includes a structural netlist of logic element primitives and their electrical connections, and binary Bitstream data representing the FPGA's physical semiconductor resource configuration. A storage device maintains a database of generated Placelist and Bitstream expectations, each representing individual physical or logical resources and their locations on the FPGA. A processor generates encoded or encrypted Placelist and Bitstream expectations, stores them in the database, and compares them to identify matches and mismatches. The comparison results indicate the trustworthiness of the FPGA design, determining whether the design intent is correctly captured and translated. The output provides verification or validation information based on the comparison, ensuring design integrity without revealing proprietary details. This approach protects intellectual property while confirming the accuracy of the FPGA design representation.
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January 26, 2021
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