Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. An Island-Based Network Flow Processor (IB-NFP) integrated circuit comprising: a plurality of processor islands, wherein each of the processor islands is of identical rectangular shape, wherein each processor island comprises a processor; a plurality of Multi-threaded Transactional Memory (MTM) islands, wherein each of the MTM islands is of identical rectangular shape, wherein each MTM island comprises an MTM; a packet ingress island of a rectangular shape, wherein the packet ingress island comprises packet ingress circuitry; a packet egress island of a rectangular shape, wherein the packet egress island comprises packet egress circuitry; and a configurable mesh posted transaction data bus that is operatively coupled to each of the processor islands, to each of the MTM islands, to the packet ingress island and to the packet egress island, wherein the configurable mesh posted transaction data bus comprises a configurable command mesh and a configurable data mesh, wherein the configurable command mesh comprises a plurality of crossbar switches and an associated plurality of links that interconnect the crossbar switches, wherein each crossbar switch of the configurable command mesh is directly coupled to at least six links that radiate outwardly in two-dimensional space from the crossbar switch, wherein the configurable data mesh comprises a plurality of crossbar switches and an associated plurality of links that interconnect the crossbar switches, wherein each crossbar switch of the configurable data mesh is directly coupled to at least six links that radiate outwardly in two-dimensional space from the crossbar switch, wherein the configurable mesh posted transaction data bus is configurable such that a plurality of commands can be communicated simultaneously across different parts of the configurable mesh posted transaction data bus, wherein each processor of the plurality of processor islands can issue a command bus transaction value onto the configurable mesh posted transaction data bus, and wherein each MTM of the plurality of MTM islands can issue a command bus transaction value onto the configurable mesh posted transaction data bus.
2. An integrated circuit comprising: a plurality of processors; a plurality of Multi-threaded Transactional Memories (MTMs), wherein each MTM of the plurality of MTMs includes an engine and a memory; and a configurable mesh posted transaction data bus, wherein the configurable mesh posted transaction data bus comprises a configurable command mesh and a configurable data mesh, wherein the configurable command mesh comprises a plurality of crossbar switches and an associated plurality of links that interconnect the crossbar switches, wherein the configurable data mesh comprises a plurality of crossbar switches and an associated plurality of links that interconnect the crossbar switches, wherein the configurable mesh posted transaction data bus is configurable such that a plurality of commands can be communicated simultaneously across different parts of the configurable mesh posted transaction data bus, wherein a command bus transaction value issued by one of the processors of the plurality of processors can pass across the configurable command mesh and to an MTM of the plurality of MTMs, wherein the command bus transaction value includes a reference value, wherein the MTM uses the reference value to initiate a pull of data across the configurable data mesh and to the MTM, wherein the MTM uses the data to perform an operation, wherein each processor of the plurality of processors can issue a command bus transaction value onto the configurable mesh posted transaction data bus, and wherein each MTM of the plurality of MTMs can issue a command bus transaction value onto the configurable mesh posted transaction data bus.
3. The integrated circuit of claim 2 , wherein the processor that issued the command bus transaction value uses the reference value received back from the MTM as a pull-id flag to identify a processor operation that initiated the issuing of the command bus transaction value.
4. The integrated circuit of claim 2 , wherein each link comprises a first link portion for communicating data in a first direction across the link and further comprises a second link portion for communicating data in a second direction opposite the first direction across the link, and wherein each link portion comprises a distributed credit First-In-First-Out (FIFO) structure that receives push signals from a first circuit at a first end of the distributed credit FIFO structure and receives taken signals from a second circuit at a second end of the distributed credit FIFO structure.
5. The integrated circuit of claim 2 , wherein each link comprises a first link portion and a second link portion, wherein the first link portion includes a chain of sequential logic elements for communicating data in a first direction across the link, and wherein the second link portion includes a chain of sequential logic elements for communicating data in a second direction opposite the first direction across the link, wherein all the sequential logic elements of the chain of a link portion are clocked by a common clock signal.
6. The integrated circuit of claim 2 , wherein each crossbar switch of the configurable command mesh stores configuration information, wherein the configuration information determines how the crossbar switch routes command bus transaction values passing through the crossbar switch, wherein each command bus transaction value carries information that is used by the crossbar switches through which the command bus transaction value passes to route the command bus transaction value.
7. The integrated circuit of claim 2 , wherein a command bus transaction value travels across a first link portion of a first link L 1 of the configurable command mesh from a first crossbar switch CB 1 to a second crossbar switch CB 2 , wherein the first crossbar switch CB 1 is a part of a first rectangular island I 1 of the integrated circuit, wherein the second crossbar switch CB 2 is a part of a second rectangular island I 2 of the integrated circuit, wherein the command bus transaction value includes a final destination portion, wherein a Look Up Table (LUT) circuit in the second crossbar switch CB 2 receives the final destination portion and outputs a corresponding lookup value, wherein the corresponding lookup value determines another link portion to which CB 2 couples the first link portion such that the command bus transaction value travels out of the second rectangular island I 2 across the another link portion.
8. The integrated circuit of claim 2 , wherein some of the links of the configurable command mesh are oriented to be collinear with respect to one another and to extend in a first direction, wherein others of the links of the configurable command mesh are oriented to be collinear with respect to one another and to extend in a second direction, wherein the first and second directions are not perpendicular to one another, and wherein the first and second directions are not parallel to one another.
9. The integrated circuit of claim 2 , wherein the engine is a lookup engine, wherein the operation performed by the MTM is a lookup operation, wherein the MTM uses the data to generate a data result, and wherein the MTM completes the lookup operation by pushing the data result from the MTM across the configurable data mesh.
10. The integrated circuit of claim 2 , wherein each crossbar switch of the configurable command mesh is directly coupled to at least six links that radiate outwardly in two-dimensional space from the crossbar switch.
11. The integrated circuit of claim 2 , wherein none of the MTMs includes any processor that fetches instructions from a memory, decodes the instructions, and executes the instructions.
12. The integrated circuit of claim 2 , wherein the integrated circuit comprises a plurality of functional circuits, wherein the configurable mesh posted transaction data bus is configurable such that a first command bus transaction value can pass from a first functional circuit to a second functional circuit through a first path of the configurable mesh posted transaction data bus and such that a second command bus transaction value can pass from a third functional circuit to a fourth functional circuit through a second path of the configurable mesh posted transaction data bus, and wherein the first command bus transaction value can travel through the first path at the same time that the second command bus transaction value travels through the second path.
13. The integrated circuit of claim 12 , wherein the first functional circuit includes a first processor of the plurality of processors, wherein the second functional circuit includes a first MTM of the plurality of MTMs, wherein the third functional circuit includes a second processor of the plurality of processors, wherein the fourth functional circuit includes a second MTM of the plurality of MTMs.
14. The integrated circuit of claim 2 , wherein each crossbar switch of the configurable command mesh is coupled to a corresponding functional circuit of the integrated circuit, wherein each functional circuit is part of a corresponding one of a plurality of rectangular islands, wherein some of the rectangular islands that include a functional circuit coupled to a crossbar switch are disposed in a first row, wherein others of the rectangular islands that include a functional circuit coupled to a crossbar switch are disposed in a second row, and wherein others of the rectangular islands that include a functional circuit coupled to a crossbar switch are disposed in a third row.
15. The integrated circuit of claim 2 , wherein at least two of the MTMs of the plurality of MTMs are substantially structurally identical, wherein the engine of one of the at least two MTMs comprises a state machine selector circuit, a plurality of state machines, and a pipeline, wherein a command is received onto the MTM from the configurable mesh posted transaction data bus, and wherein the state machine selector circuit then allocates execution of the command to a selected one of the plurality of state machines such that the selected state machine then interacts with the pipeline to carry out the command.
This invention relates to integrated circuits with multiple transaction managers (MTMs) for handling data transactions in a configurable mesh network. The problem addressed is the efficient and scalable management of data transactions in complex integrated circuits, particularly in systems requiring high throughput and low latency. The integrated circuit includes a plurality of MTMs, where at least two of these MTMs are structurally identical. Each MTM contains an engine that processes commands received from a configurable mesh posted transaction data bus. The engine includes a state machine selector circuit, multiple state machines, and a pipeline. When a command is received, the state machine selector circuit allocates the command to a specific state machine, which then interacts with the pipeline to execute the command. This design allows for parallel processing of transactions, improving efficiency and reducing bottlenecks in data handling. The use of structurally identical MTMs ensures consistency and simplifies design verification, while the state machine selector circuit enables dynamic allocation of tasks, optimizing resource utilization. The pipeline further enhances performance by breaking down commands into sequential stages, allowing for concurrent execution of different operations. This architecture is particularly useful in high-performance computing, networking, and data processing applications where transaction management must be both scalable and efficient.
16. An integrated circuit comprising: a plurality of processor islands, wherein each of the processor islands is of identical rectangular shape, wherein each processor island comprises a processor; a plurality of Multi-threaded Transactional Memory (MTM) islands, wherein each of the MTM islands is of identical rectangular shape, wherein each MTM island comprises an MTM; and a configurable mesh posted transaction data bus, wherein the configurable mesh posted transaction data bus comprises a configurable command mesh and a configurable data mesh, wherein the configurable command mesh comprises a plurality of crossbar switches and an associated plurality of links that interconnect the crossbar switches, wherein the configurable data mesh comprises a plurality of crossbar switches and an associated plurality of links that interconnect the crossbar switches, wherein the configurable mesh posted transaction data bus is configurable such that a plurality of commands can be communicated simultaneously across different parts of the configurable mesh posted transaction data bus, wherein each processor of the plurality of processor islands can issue a command bus transaction value onto the configurable mesh posted transaction data bus, and wherein each MTM of the plurality of MTM islands can issue a command bus transaction value onto the configurable mesh posted transaction data bus.
17. The integrated circuit of claim 16 , wherein each link comprises a first link portion and a second link portion, wherein the first link portion includes a chain of sequential logic elements for communicating data in a first direction across the link, and wherein the second link portion includes a chain of sequential logic elements for communicating data in a second direction opposite the first direction across the link, and wherein all the sequential logic elements of the chain of a link portion are clocked by a common clock signal.
18. The integrated circuit of claim 16 , wherein each link comprises a first link portion for communicating data in a first direction across the link and further comprises a second link portion for communicating data in a second direction opposite the first direction across the link, and wherein each link portion comprises a distributed credit First-In-First-Out (FIFO) structure that receives push signals from a first circuit at a first end of the distributed credit FIFO structure and receives taken signals from a second circuit at a second end of the distributed credit FIFO structure.
19. The integrated circuit of claim 16 , wherein each of the links of the configurable command mesh extends in a substantially straight line, wherein some of the links of the configurable command mesh are oriented to be collinear with respect to one another and to extend in a first direction, wherein others of the links of the configurable command mesh are oriented to be collinear with respect to one another and to extend in a second direction, wherein the first and second directions are not perpendicular to one another, and wherein the first and second directions are not parallel to one another.
20. The integrated circuit of claim 16 , wherein a command bus transaction value travels across a first link portion of a first link L 1 of the configurable command mesh from a first crossbar switch CB 1 to a second crossbar switch CB 2 , wherein the first crossbar switch CB 1 is a part of a first island I 1 , wherein the second crossbar switch CB 2 is a part of a second island I 2 , wherein the command bus transaction value includes a final destination portion, wherein a Look Up Table (LUT) circuit in the second crossbar switch CB 2 receives the final destination portion and outputs a corresponding lookup value, wherein the corresponding lookup value determines another link portion to which CB 2 couples the first link portion such that the command bus transaction value travels out of the second island I 2 across the another link portion.
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February 2, 2021
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