Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A data storage device, comprising: a memory device; and a controller coupled to the memory device, the controller configured to: receive user write performance preference data for two or more logical block addresses (LBAs) to be written; receive a first write command for a first LBA of the two or more LBAs; receive a second write command for a second LBA of the two or more LBAs, wherein a flash translation layer (FLT) maps LBAs to word lines; determine whether current word line of the memory device is a word line that needs enhanced post write read (EPWR); and write the second LBA to the current word line, wherein the first LBA remains in a buffer while the second LBA is written.
2. The data storage device of claim 1 , wherein the second LBA has a write performance preference that is higher than the write performance preference for the first LBA.
3. The data storage device of claim 2 , wherein the current word line needs EPWR.
4. The data storage device of claim 3 , wherein the current word line does not need EPWR and wherein the next word line needs EPWR.
5. The data storage device of claim 1 , wherein the user write preferences are stored in RAM.
6. The data storage device of claim 1 , wherein the controller is further configured to update a translation table of the flash translation layer (FTL) regarding the second LBA being written prior to the first LBA.
7. The data storage device of claim 1 , wherein the controller is further configured to write the first LBA to another word line of the memory device and perform EPWR on the written first LBA.
The invention relates to data storage devices, specifically non-volatile memory systems like solid-state drives (SSDs) that use error-prone write recovery (EPWR) techniques to handle data corruption during write operations. The problem addressed is ensuring data integrity when write errors occur in memory devices, particularly in flash storage where bit errors can arise due to wear, interference, or other factors. The data storage device includes a controller and a memory device with multiple word lines. The controller is configured to detect a write error when writing data to a first logical block address (LBA) on a word line. Upon detecting the error, the controller performs EPWR by rewriting the corrupted data to the same word line or a different word line in the memory device. This process may involve error correction, verification, and retry mechanisms to ensure the data is correctly stored. The invention improves reliability by dynamically handling write errors without requiring immediate intervention from higher-level systems, reducing data loss and performance degradation. The controller may also log error events for diagnostic purposes and adjust write parameters to mitigate future errors. This approach is particularly useful in high-density memory systems where error rates are higher.
8. A data storage device, comprising: a memory device; and a controller coupled to the memory device, the controller configured to: determine whether a first LBA of a plurality of LBAs has a write performance preference; determine whether a second LBA of the plurality of LBAs have a write performance preference; determine whether a current word line of the memory device needs enhanced post write read (EPWR); and determine whether to write the second LBA to the current word line prior to writing the first LBA to the memory device.
9. The data storage device of claim 8 , wherein the controller is configured to determine that the first LBA has a preferred write performance preference.
A data storage device includes a non-volatile memory and a controller. The controller manages data storage operations by assigning logical block addresses (LBAs) to physical memory locations. The controller is configured to determine that a first LBA has a preferred write performance preference, meaning it prioritizes faster write operations for this LBA. The controller then selects a first physical memory location with a first write performance characteristic that matches the preferred write performance preference of the first LBA. The controller writes data to the first physical memory location based on this preference. The device may also include a second LBA with a different write performance preference, and the controller selects a second physical memory location with a second write performance characteristic that matches the second LBA's preference. The controller may further track the write performance characteristics of physical memory locations and update this information over time. The device ensures that data is stored in locations that align with the performance requirements of the LBAs, optimizing write operations for different performance needs.
10. The data storage device of claim 9 , wherein the controller is configured to determine that the second LBA does not have a write performance preference.
11. The data storage device of claim 10 , wherein the controller is configured to determine that the current word line needs EPWR.
12. The data storage device of claim 11 , wherein the controller is configured to write the second LBA to the current word line with EPWR.
13. The data storage device of claim 8 , wherein the controller is configured to determine that the first LBA does not have a preferred write performance preference.
14. The data storage device of claim 13 , wherein the controller is configured to determine that the second LBA has a write performance preference.
15. The data storage device of claim 14 , wherein the controller is configured to determine that the current word line needs EPWR.
16. The data storage device of claim 15 , wherein the controller is configured to write the first LBA to the current word line with EPWR.
A data storage device, such as a solid-state drive (SSD) or flash memory device, is designed to improve write performance and reliability by dynamically adjusting write parameters based on the logical block address (LBA) being written. The device includes a controller that manages data storage operations across multiple memory blocks, each containing multiple word lines. The controller is configured to write data to a specific word line using a first write parameter, such as a program voltage or write speed, when the LBA being written belongs to a first group of LBAs. This group may correspond to frequently accessed or critical data. For another group of LBAs, the controller uses a second write parameter, which may prioritize endurance or speed over reliability. The controller dynamically selects the appropriate write parameter based on the LBA's characteristics, such as access frequency or data importance, to optimize performance and longevity. The invention ensures that critical data is written with higher reliability while less critical data is handled more efficiently, balancing overall system performance and endurance. This approach is particularly useful in storage systems where different data types require varying levels of reliability and speed.
17. A data storage device, comprising: a memory device; means to determine whether LBAs have write performance preferences; means to determine whether a current word line of the memory device needs enhanced post write read (EPWR); and means to write LBAs to the current word line out of order based upon write performance preferences.
18. The data storage device of claim 17 , further comprising means to update a translation table of a flash translation layer (FTL) based upon the means to write LBAs to the current word line out of order.
19. The data storage device of claim 17 , further comprising: means to receive user write performance preferences for LBAs; and means to store user write performance preferences for LBAs.
20. The data storage device of claim 17 , wherein the means to write LBAs to the current word line out of order is also based upon whether the current word line of the memory device needs EPWR.
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February 16, 2021
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