Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A memory device comprising: a first CAM block and a second CAM block, in which a micro-code is stored; and a control logic configured to control the first and second CAM blocks such that the stored micro-code is updated with a new micro-code in a micro-code update operation, wherein the control logic includes: a command interface configured to control program and read operations of the first CAM block and the second CAM block in response to a command received from the outside; a first memory configured to store an algorithm for performing the read operation of the micro-code stored in the first CAM block, and output read only memory (ROM) data, based on the algorithm, in an initialization operation; a second memory configured to store the micro-code read from the first CAM block in the initialization operation, and output random access memory (RAM) data, based on the stored micro-code; a selection circuit configured to select and output the ROM data output from the first memory in the initialization operation, and select and output the RAM data output from the second memory in a normal operation; and an instruction decoder configured to receive the ROM data or the RAM data, which is output from the selection circuit, to generate control signals for performing an operation.
2. The memory device of claim 1 , wherein the first memory is configured with a ROM, and the second memory is configured with a RAM.
3. The memory device of claim 1 , further comprising a peripheral circuit configured to perform the program operation and the read operation on the first CAM block and the second CAM block.
4. The memory device of claim 3 , wherein the peripheral circuit stores the micro-code in a plurality of pages included in each of the first CAM block and the second CAM block, and wherein a plurality of same micro-codes are programmed to be stored in each of the plurality of pages.
This invention relates to memory devices, specifically those incorporating content-addressable memory (CAM) blocks for storing micro-code. The problem addressed is the efficient storage and retrieval of micro-code in memory devices, particularly in systems where redundancy and reliability are critical. The memory device includes a peripheral circuit and at least two CAM blocks—first and second CAM blocks—each storing micro-code. The peripheral circuit manages the storage and retrieval of this micro-code. The micro-code is organized into multiple pages within each CAM block, with identical copies of the same micro-code programmed into each page. This redundancy ensures that if one page fails or becomes corrupted, the micro-code remains accessible from another page, improving reliability. The peripheral circuit can access the micro-code from any of the redundant pages, allowing for seamless operation even in the presence of errors. This approach enhances fault tolerance and data integrity in memory systems where micro-code is critical for device operation. The redundant storage of micro-code across multiple pages in separate CAM blocks ensures that the system can continue functioning correctly even if one or more pages fail.
5. The memory device of claim 4 , wherein the peripheral circuit reads the plurality of same micro-codes as one micro-code through a majority check in the read operation on the first CAM block.
6. The memory device of claim 2 , wherein the micro-code is configured with main micro-code data, sub micro-code data, a Cyclic Redundancy Check (CRC code, and random data.
A memory device includes a micro-code storage unit that stores micro-code data for controlling operations of the device. The micro-code is structured with main micro-code data, which contains primary control instructions, and sub micro-code data, which includes supplementary or conditional instructions. The micro-code also incorporates a Cyclic Redundancy Check (CRC) code to verify data integrity and detect errors during execution. Additionally, the micro-code includes random data, which may serve as padding or for security purposes, such as obfuscation or anti-tampering measures. The memory device may further include a micro-code execution unit that processes the stored micro-code to perform operations like data access, error correction, or security checks. The CRC code ensures that the micro-code remains uncorrupted, while the random data may prevent reverse engineering or unauthorized modifications. This structured approach improves reliability, security, and flexibility in memory device operations.
7. The memory device of claim 6 , wherein the second memory stores only the main micro-code data and the sub micro-code data in the micro-code.
8. A memory system comprising: a memory device including a plurality of semiconductor memories, wherein each of the plurality of semiconductor memories performs an operation based on a micro-code; and a controller configured to receive a micro-code update command and a new micro-code from a host, and transmit the micro-code update command and the new micro-code to the memory device, wherein each of the plurality of semiconductor memories stores the new micro-code received from the controller in first and second CAM blocks in a micro-code update operation, and reads the new micro-code stored in the first CAM block and then load the read new micro-code into an algorithm dedicated random access memory (RAM) in an initialization operation, and wherein each of the plurality of semiconductor memories includes: the first CAM block and the second CAM block, in which the micro-code is stored; a plurality of memory blocks; a peripheral circuit configured to perform a program operation and a read operation on the first CAM block and the second CAM block; and a control logic configured to control the peripheral circuit to perform an operation on the plurality of memory blocks, and store the new micro-code in the second CAM block and copy the new micro-code from the second CAM block into the first CAM block in the micro-code update operation.
9. The memory system of claim 8 , wherein the control logic includes: a CAM block control circuit configured to control the program operation and the read operation of the first CAM block and the second CAM block; a CAM read dedicated ROM configured to store an algorithm for performing the read operation of the micro-code stored in the first CAM block, and output ROM data, based on the algorithm in the initialization operation; an algorithm dedicated RAM configured to store the micro-code read from the first CAM block in the initialization operation, and output RAM data, based on the micro-code, in the general operation; and an instruction decoder configured to selectively receive the ROM data and the RAM data to generate control signals for controlling the peripheral circuit.
10. The memory system of claim 9 , wherein the control logic further includes a selection circuit configured to transmit the ROM data to the instruction decoder in the initialization operation, and transmit the RAM data to the instruction decoder in the general operation.
11. The memory system of claim 8 , wherein the peripheral circuit stores the micro-code in a plurality of pages included in each of the first CAM block and the second CAM block, and wherein a plurality of same micro-codes are programmed to be stored in each of the plurality of pages.
12. The memory system of claim 11 , wherein the peripheral circuit reads the plurality of same micro-codes as one micro-code through a majority check in the read operation on the first CAM block.
13. The memory system of claim 9 , wherein the micro-code is configured with main micro-code data, sub micro-code data, a CRC code, and random data.
14. The memory system of claim 13 , wherein the algorithm dedicated RAM stores only the main micro-code data and the sub micro-code data in the micro-code.
15. A method for operating a memory device, the method comprising: receiving a micro-code update command and a new micro-code from a host; storing the new micro-code in a second CAM block of a semiconductor memory in response to the micro-code update command; performing an operation of erasing a first CAM block in which an original micro-code is stored, and copying the new micro-code from the second CAM block to the first CAM block; performing a read operation of the first CAM block based on an algorithm stored in a CAM read dedicated ROM in an initialization operation; selecting read only memory (ROM) data outputted from the CAM read dedicated ROM in the initialization operation; storing a micro-code read from the first CAM block in an algorithm dedicated RANI; selecting RAM data outputted from the algorithm dedicated RAM during a normal operation; and controlling a peripheral circuit, based on the micro-code stored in the algorithm dedicated RAM in the normal operation.
This invention relates to a method for updating and managing micro-code in a semiconductor memory device, particularly addressing the need for reliable and efficient micro-code updates without disrupting normal operations. The method involves receiving a micro-code update command and new micro-code from a host system, which is then stored in a secondary content-addressable memory (CAM) block. The original micro-code, stored in a primary CAM block, is erased, and the new micro-code is copied from the secondary CAM block to the primary CAM block. During initialization, the device reads the micro-code from the primary CAM block using an algorithm stored in a dedicated CAM read-only memory (ROM). The read micro-code is then stored in an algorithm-dedicated random-access memory (RAM). During normal operation, the device selects data from this RAM and uses it to control peripheral circuits. The method ensures seamless micro-code updates while maintaining system stability and performance. The use of separate CAM blocks and dedicated ROM/RAM components optimizes the update process and ensures reliable execution of the micro-code.
16. The method of claim 15 , wherein, when a status fail of the first CAM block occurs as a result obtained by performing the copy operation, the second CAM block is defined as an original micro-code block, and a convergence block operation of erasing the first CAM block is performed.
17. The method of claim 15 , wherein a majority check operation is performed on the micro-code read from the first CAM block.
18. The method of claim 15 , wherein the micro-code stored in the first CAM block includes main micro-code data, sub micro-code data, a Cyclic Redundancy Check (CRC) code, and random data, and wherein the micro-code stored in the algorithm dedicated RAM includes only the main micro-code data and the sub micro-code data.
This invention relates to a system for managing micro-code storage and execution in a computing device, particularly addressing the challenge of efficiently storing and retrieving micro-code while ensuring data integrity and security. The system involves a content-addressable memory (CAM) block and an algorithm-dedicated random-access memory (RAM) to store and execute micro-code instructions. The CAM block stores micro-code data, including main micro-code data, sub micro-code data, a Cyclic Redundancy Check (CRC) code for error detection, and random data for security purposes. The algorithm-dedicated RAM, however, stores only the main and sub micro-code data, omitting the CRC and random data to optimize storage and retrieval efficiency. This separation allows the system to verify the integrity of the micro-code using the CRC stored in the CAM block while reducing the storage overhead in the RAM. The system ensures that only valid and secure micro-code is executed, enhancing reliability and performance in computing operations. The invention is particularly useful in environments where micro-code integrity and efficient storage are critical, such as in embedded systems or specialized processing units.
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February 23, 2021
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