Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A hardware device comprising: a compare unit at one level of a plurality of levels of a hierarchical structure to be used in sorting of records, the compare unit comprising a buffer pair in which one or more buffers of the buffer pair are adapted to store at least one record; and another compare unit on another level of the plurality of levels of the hierarchical structure, the another level of the plurality of levels being a different level than the one level of the plurality of levels, the another compare unit on the another level of the plurality of levels comprising another buffer pair in which one or more other buffers of the another buffer pair are adapted to store a portion of a record, wherein a size of the one or more other buffers of the another buffer pair is different from a size of the one or more buffers of the buffer pair, wherein the size of the one or more other buffers of the another buffer pair is reduced compared to the size of the one or more buffers of the buffer pair and is insufficient to store the record; and wherein the one compare unit and the another compare unit are adapted to sort a plurality of records.
2. The hardware device of claim 1 , wherein the one level of the plurality of levels is a top level of the hierarchical structure, and the another level of the plurality of levels is a lower level of the hierarchical structure.
This invention relates to a hardware device designed to manage and process data within a hierarchical structure. The device addresses the challenge of efficiently organizing and accessing data across multiple levels of a hierarchy, particularly when navigating from a top-level to a lower-level structure. The hardware device includes a memory configured to store data in a hierarchical structure with multiple levels, where each level contains data elements linked to elements in adjacent levels. The device further includes a processor that executes instructions to perform operations on the data, such as retrieving, modifying, or transferring data between levels. Specifically, the device is configured to handle interactions between a top-level and a lower-level of the hierarchy, ensuring seamless data flow and consistency across these levels. The processor may also include specialized logic circuits to optimize performance for hierarchical data operations, such as caching frequently accessed data or pre-processing data before transfer between levels. The device may be used in systems requiring structured data management, such as databases, file systems, or network routing, where maintaining hierarchical relationships is critical for efficient operation. The invention improves data access speed and reduces computational overhead by leveraging hardware-accelerated processing tailored to hierarchical structures.
3. The hardware device of claim 1 , wherein the size of the one or more other buffers of the another buffer pair is at least a maximum size of a key of a record of the plurality of records.
4. The hardware device of claim 3 , wherein the size of the one or more other buffers of the another buffer pair is at least twice the maximum size of the key.
A hardware device is designed to optimize data processing in systems where key-value pairs are frequently accessed, such as in databases or caching systems. The device includes multiple buffer pairs, each consisting of a primary buffer and one or more secondary buffers. The primary buffer stores frequently accessed key-value pairs, while the secondary buffers store additional key-value pairs that are less frequently accessed. The secondary buffers are sized to be at least twice the maximum size of the key, ensuring efficient storage and retrieval of key-value pairs. This design reduces latency by minimizing the need to access slower memory systems, such as disk storage, for frequently accessed data. The hardware device dynamically manages buffer allocation based on access patterns, prioritizing frequently accessed keys in the primary buffer while maintaining less frequently accessed keys in the secondary buffers. This approach improves overall system performance by reducing the time required to retrieve key-value pairs from slower storage media. The device is particularly useful in high-performance computing environments where low-latency data access is critical.
5. The hardware device of claim 1 , wherein a selected buffer of the one or more other buffers stores a key of the record, and wherein data of the record is stored in one or more selected buffers on one or more other levels of the plurality of levels.
This invention relates to a hardware device for managing data storage in a hierarchical buffer system. The device addresses the challenge of efficiently storing and retrieving records in a multi-level buffer architecture, where data is distributed across multiple buffers at different levels to optimize access speed and storage capacity. The hardware device includes a plurality of buffers organized into multiple levels, where each level contains one or more buffers. A selected buffer at a given level stores a key associated with a record, while the actual data of the record is distributed across one or more buffers at other levels. This separation of keys and data allows for faster key-based lookups while maintaining efficient data storage. The hierarchical structure enables the device to prioritize frequently accessed data by placing it in higher-level buffers, reducing latency for critical operations. The device dynamically manages buffer allocation, ensuring that keys and corresponding data are stored in optimal locations based on access patterns. This approach improves overall system performance by minimizing redundant data transfers and reducing the need for frequent buffer flushes. The invention is particularly useful in high-performance computing environments where low-latency data access is critical, such as in databases, caching systems, or memory management units. The hierarchical buffer system balances speed and capacity, making it suitable for applications requiring both rapid access and large-scale data storage.
6. The hardware device of claim 5 , wherein one or more compare units of the hierarchical structure are configured to use one or more control indicators to enable the data of the record to flow through the hierarchical structure, based on a key associated with the data being determined a winner key in a compare.
7. The hardware device of claim 1 , wherein at least one buffer of the one or more other buffers is implemented as a ring buffer.
8. The hardware device of claim 1 , wherein at least one compare unit of the compare unit and the another compare unit includes an array of buffer pairs having a plurality of buffer pairs that provide input to the at least one compare unit, and wherein the hardware device further comprises a set of arrays to be used to access one or more buffer pairs of the plurality of buffer pairs of the array during a sort.
The invention relates to a hardware device designed for efficient data comparison and sorting operations. The device addresses the problem of optimizing comparison and sorting processes in hardware, particularly in systems requiring high-speed data processing. The hardware device includes at least two compare units, each configured to compare data elements and generate comparison results. At least one of these compare units incorporates an array of buffer pairs, where each buffer pair stores input data for comparison. The buffer pairs are organized in a structured array to facilitate rapid access during sorting operations. Additionally, the device includes a set of arrays that enable selective access to specific buffer pairs within the array during sorting, improving efficiency and reducing latency. This design allows the hardware device to perform parallel comparisons and sorting operations, enhancing overall system performance in applications such as data processing, networking, and real-time analytics. The use of buffer pairs and dedicated arrays ensures that data is efficiently managed and compared, minimizing bottlenecks and maximizing throughput.
9. The hardware device of claim 8 , wherein the set of arrays comprises a write address array, the write address array comprising a first write incremental address and a second write incremental address to indicate an offset into a buffer of a select buffer pair of the plurality of buffer pairs to be written.
10. The hardware of claim 8 , wherein the set of arrays comprises a read address array, the read address array comprising a first read incremental address and a second read incremental address to indicate an offset into a select buffer of a select buffer pair of the plurality of buffer pairs to be read.
11. An integrated circuit comprising: a field programmable gate array, the field programmable gate array comprising: a compare unit at one level of a plurality of levels of a hierarchical structure to be used in sorting of records, the compare unit comprising a buffer pair in which one or more buffers of the buffer pair are adapted to store at least one record; and another compare unit on another level of the plurality of levels of the hierarchical structure, the another level of the plurality of levels being a different level than the one level of the plurality of levels, the another compare unit on the another level of the plurality of levels comprising another buffer pair in which one or more other buffers of the another buffer pair are adapted to store a portion of a record, wherein a size of the one or more other buffers of the another buffer pair is different from a size of the one or more buffers of the buffer pair, wherein the size of the one or more other buffers of the another buffer pair is reduced compared to the size of the one or more buffers of the buffer pair and is insufficient to store the record; and wherein the one compare unit and the another compare unit are adapted to sort a plurality of records.
12. The integrated circuit of claim 11 , wherein the one level of the plurality of levels is a top level of the hierarchical structure, and the another level of the plurality of levels is a lower level of the hierarchical structure.
13. The integrated circuit of claim 11 , wherein the size of the one or more other buffers of the another buffer pair is at least a maximum size of a key of a record of the plurality of records.
This invention relates to integrated circuits designed for efficient data processing, particularly in systems handling large datasets with variable-length records. The problem addressed is optimizing buffer management to prevent data overflow and ensure smooth processing of records with keys of varying sizes. The integrated circuit includes multiple buffer pairs, where each pair consists of a primary buffer and one or more secondary buffers. The primary buffer is used for storing a record, while the secondary buffers handle additional data or metadata associated with the record. A key aspect of the invention is that the size of the secondary buffers in each buffer pair is at least as large as the maximum possible size of a key within any record processed by the system. This ensures that even the largest keys can be accommodated without causing buffer overflow, thereby maintaining system stability and performance. The design allows for flexible handling of records with different key sizes while minimizing the risk of data corruption or processing delays. The integrated circuit may also include control logic to manage buffer allocation and data flow, ensuring efficient use of resources and preventing bottlenecks. This approach is particularly useful in high-speed data processing applications where reliability and performance are critical.
14. The integrated circuit of claim 13 , wherein the size of the one or more other buffers of the another buffer pair is at least twice the maximum size of the key.
15. The integrated circuit of claim 11 , wherein a selected buffer of the one or more other buffers stores a key of the record, and wherein data of the record is stored in one or more selected buffers on one or more other levels of the plurality of levels.
This invention relates to an integrated circuit designed for efficient data storage and retrieval, particularly in systems requiring hierarchical memory structures. The problem addressed is optimizing memory access by distributing data across multiple levels of buffers, reducing latency and improving performance in applications like databases or caching systems. The integrated circuit includes a plurality of buffers organized into multiple hierarchical levels. Each level contains one or more buffers, and data is distributed across these levels based on access patterns or priority. A key component is the ability to store a record's key in a selected buffer at one level while storing the corresponding data in one or more buffers at other levels. This separation allows for faster key-based lookups while maintaining efficient data storage. The system dynamically selects buffers for key and data storage based on factors like access frequency or memory constraints, ensuring optimal performance. The hierarchical structure enables scalable and flexible memory management, suitable for high-performance computing environments. The invention improves upon prior art by reducing redundant data storage and minimizing access delays through intelligent buffer allocation.
16. The integrated circuit of claim 15 , wherein one or more compare units of the hierarchical structure are configured to use one or more control indicators to enable the data of the record to flow through the hierarchical structure, based on a key associated with the data being determined a winner key in a compare.
This invention relates to an integrated circuit designed for efficient data processing in hierarchical structures, particularly for systems requiring rapid comparison and routing of data records. The circuit addresses the challenge of managing large datasets where records must be compared and filtered based on key values, ensuring only relevant data flows through the system. The hierarchical structure includes multiple compare units that evaluate records against a key, determining whether the key is a "winner" in a comparison. When a key is identified as a winner, control indicators are used to enable the corresponding data record to proceed through the hierarchical structure, while non-winning records are filtered out. This selective routing improves processing efficiency by reducing unnecessary data movement and enabling parallel comparisons. The circuit is particularly useful in applications such as network packet filtering, database sorting, or real-time data analysis, where fast and scalable data handling is critical. The hierarchical design allows for modular expansion, accommodating varying data volumes and complexity. The use of control indicators ensures precise control over data flow, minimizing latency and resource consumption.
17. The integrated circuit of claim 11 , wherein at least one compare unit of the compare unit and the another compare unit includes an array of buffer pairs having a plurality of buffer pairs that provide input to the at least one compare unit, and wherein the field programmable gate array further comprises a set of arrays to track which one or more buffer pairs of the plurality of buffer pairs of the array are to be accessed during a sort.
18. The integrated circuit of claim 17 , wherein the set of arrays comprises a write address array, the write address array comprising a first write incremental address and a second write incremental address to indicate an offset into a buffer of a select buffer pair of the plurality of buffer pairs to be written.
19. The integrated circuit of claim 17 , wherein the set of arrays comprises a read address array, the read address array comprising a first read incremental address and a second read incremental address to indicate an offset into a buffer of a select buffer pair of the plurality of buffer pairs to be read.
20. A method comprising: providing a compare unit at one level of a plurality of levels of a hierarchical structure to be used in sorting of records, the compare unit comprising a buffer pair in which one or more buffers of the buffer pair are adapted to store at least one record; providing another compare unit on another level of the plurality of levels of the hierarchical structure, the another level of the plurality of levels being a different level than the one level of the plurality of levels, the another compare unit on the another level of the plurality of levels comprising another buffer pair in which one or more other buffers of the another buffer pair are adapted to store a portion of a record, wherein a size of the one or more other buffers of the another buffer pair is different from a size of the one or more buffers of the buffer pair, wherein the size of the one or more other buffers of the another buffer pair is reduced compared to the size of the one or more buffers of the buffer pair and is insufficient to store the record; and wherein the one compare unit and the another compare unit are adapted to sort a plurality of records.
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March 2, 2021
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