Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A circuit disposed on a first circuit die, the circuit comprising: a real time clock (RTC) circuit to: receive a shared clock signal that is shared among a plurality of circuit dies including the first circuit die; receive clock information associated with the shared clock signal; generate a RTC signal, wherein a frequency of the shared clock signal is higher than a frequency of the RTC signal; and modulate the RTC signal to encode the clock information by adjustment of a pulse width of the RTC signal; provide the modulated RTC signal with a pre-defined pulse width to indicate an end of a message encoded by the modulated RTC signal; and maintain the modulated RTC signal with the pre-defined pulse width until a start of a next message; and an output terminal coupled to the RTC circuit to pass the modulated RTC signal to one or more other circuit dies of the plurality of circuit dies.
This invention relates to integrated circuit timing synchronization, specifically addressing the challenge of efficiently distributing clock information across multiple circuit dies while minimizing power consumption and complexity. The system includes a real-time clock (RTC) circuit integrated into a first circuit die. The RTC circuit receives a shared clock signal, which is distributed among multiple circuit dies, including the first die. The shared clock signal operates at a higher frequency than the RTC signal generated by the circuit. The RTC circuit encodes clock information by modulating the RTC signal through pulse width adjustments. A pre-defined pulse width is used to mark the end of a message encoded in the modulated RTC signal, and this pulse width is maintained until the start of the next message. The modulated RTC signal is then transmitted to other circuit dies via an output terminal. This approach enables low-power, low-complexity synchronization of clock information across multiple dies without requiring dedicated high-speed communication channels. The modulation technique ensures reliable message delineation and reduces overhead in clock distribution systems.
2. The circuit of claim 1 , wherein the RTC circuit is to generate the RTC signal based on the shared clock signal.
A circuit includes a real-time clock (RTC) circuit and a shared clock signal generator. The shared clock signal generator produces a clock signal that is distributed to multiple components, including the RTC circuit. The RTC circuit generates an RTC signal based on the shared clock signal, ensuring synchronized timing across the system. The shared clock signal may be derived from an external or internal clock source, and the RTC circuit uses this signal to maintain accurate timekeeping. The circuit may also include additional components, such as a processor or memory, that rely on the shared clock signal for coordinated operation. The RTC circuit's reliance on the shared clock signal reduces the need for a dedicated clock source, improving efficiency and reducing complexity. The system ensures precise timing synchronization between the RTC and other clock-dependent components, which is critical for applications requiring accurate timekeeping, such as embedded systems, IoT devices, or communication protocols. The shared clock signal may be adjustable in frequency or duty cycle to accommodate different operational requirements. The RTC circuit may further include calibration mechanisms to compensate for clock drift, ensuring long-term accuracy. The overall design optimizes power consumption and minimizes hardware overhead by leveraging a single clock source for multiple timing functions.
3. The circuit of claim 1 , wherein the clock information indicates a temperature associated with a clock circuit that generates the shared clock signal.
A circuit includes a clock distribution network that provides a shared clock signal to multiple integrated circuits (ICs) or components. The clock signal is synchronized across the system to ensure timing consistency. The circuit also includes a mechanism to transmit clock information, such as phase, frequency, or other timing parameters, to receiving devices. This information allows the receiving devices to adjust their internal timing or operations based on the shared clock signal. In one embodiment, the clock information includes temperature data associated with the clock circuit that generates the shared clock signal. By monitoring the temperature of the clock circuit, the system can compensate for thermal variations that may affect clock signal stability or performance. This temperature data may be used to adjust clock signal generation, distribution, or synchronization to maintain accuracy and reliability in varying thermal conditions. The circuit may be part of a larger system, such as a data processing system, communication system, or other electronic device where precise timing is critical. The inclusion of temperature data in the clock information enables dynamic adjustments to ensure optimal performance under different operating conditions.
4. The circuit of claim 3 , wherein the clock circuit includes a crystal oscillator.
A circuit for generating a clock signal includes a clock circuit configured to produce a periodic output signal. The clock circuit is designed to operate in a low-power mode to conserve energy when the circuit is inactive. The circuit also includes a control circuit that monitors the periodic output signal and activates the clock circuit from the low-power mode when a specific condition is detected. The control circuit then deactivates the clock circuit back to the low-power mode after a predetermined time interval. The clock circuit includes a crystal oscillator to ensure precise timing of the periodic output signal. The control circuit may also include a counter to track the time interval and a comparator to detect the specific condition. The overall design aims to reduce power consumption while maintaining accurate timing for applications requiring periodic activation.
5. The circuit of claim 1 , wherein the RTC circuit is to adjust the pulse width by adjusting a timing of a falling edge of the RTC signal.
6. The circuit of claim 5 , wherein the RTC circuit is to provide the modulated RTC signal with a first duty cycle over a first cycle to indicate that a first bit encoded by the modulated RTC signal is a first logic value and is to provide the modulated RTC signal with a second duty cycle over a second cycle to indicate that a second bit encoded by the modulated RTC signal is a second logic value, wherein the second duty cycle is different than the first duty cycle and the second logic value is different than the first logic value.
7. The circuit of claim 5 , wherein the modulated RTC signal is to encode a plurality of bits per cycle of the modulated RTC signal based on the pulse width of the modulated RTC signal.
8. The circuit of claim 5 , wherein the modulated RTC signal further encodes a start of message indicator based on the pulse width of the modulated RTC signal.
9. The circuit of claim 5 , wherein all duty cycles of the modulated RTC signal used to encode the clock information are between 45% and 55%.
A circuit for generating a real-time clock (RTC) signal with encoded clock information uses pulse-width modulation (PWM) to represent time data. The circuit includes a clock source, a modulation circuit, and an output stage. The modulation circuit generates a modulated RTC signal by varying the duty cycle of the clock source signal to encode time information, such as hours, minutes, and seconds. The output stage provides the modulated signal to a load, such as a display or a communication interface. The duty cycle of the modulated RTC signal is constrained to a narrow range between 45% and 55% to ensure reliable decoding of the encoded clock information. This range minimizes errors in time data extraction while maintaining signal integrity. The circuit may also include error correction mechanisms to further enhance accuracy. The modulated RTC signal can be transmitted over a communication channel or used locally within a device. The narrow duty cycle range ensures compatibility with standard decoding circuits and reduces susceptibility to noise and interference. The invention is particularly useful in applications requiring precise timekeeping, such as industrial control systems, telecommunications, and embedded devices.
10. A system comprising: a crystal oscillator to generate a shared clock signal; a plurality of circuit dies having respective circuitry, the plurality of circuit dies including a first circuit die having: a real time clock (RTC) circuit to: receive a shared clock signal that is shared among the plurality of circuit dies; receive clock information associated with the shared clock signal; generate a modulated RTC signal based on the shared clock signal, wherein the modulated RTC signal is modulated using pulse width modulation to encode the clock information, and wherein a frequency of the modulated RTC signal is less than a frequency of the shared clock signal; provide the modulated RTC signal with a pre-defined pulse width to indicate an end of a message encoded by the modulated RTC signal; and maintain the modulated RTC signal with the pre-defined pulse width until a start of a next message; and pass the modulated RTC signal to one or more other circuit dies of the plurality of circuit dies.
11. The system of claim 10 , wherein the system further comprises a temperature sensor to detect a temperature value associated with the crystal oscillator, and wherein the clock information includes the detected temperature value.
12. The system of claim 10 , wherein the RTC circuit is to generate the modulated RTC signal using pulse width modulation by adjusting a timing of a falling edge of the modulated RTC signal to indicate the encoded clock information while maintaining a timing of a rising edge of the modulated RTC signal.
13. The system of claim 10 , wherein the modulated RTC signal is to encode a plurality of bits per cycle of the modulated RTC signal based on a pulse width of the modulated RTC signal.
14. The system of claim 10 , wherein a duty cycle of the modulated RTC signal varies between a range of values that are between 45% and 55%.
15. The system of claim 10 , wherein the plurality of circuit dies include a processor, a cellular radio frequency (RF) die, and a connectivity (CNV) die.
16. A circuit disposed on a first circuit die, the circuit comprising: a first input terminal to receive a shared clock signal from a second circuit die; a second input terminal to receive a modulated real time clock (RTC) signal that encodes clock information associated with the shared clock signal, wherein a frequency of the modulated RTC signal is less than a frequency of the shared clock signal, wherein the modulated RTC signal has a pre-defined pulse width to indicate an end of a message encoded by the modulated RTC signal, and wherein the pre-defined pulse width is maintained until a start of a next message; and a decoder to decode the clock information from the modulated RTC signal.
17. The circuit of claim 16 , wherein the modulated RTC signal is encoded using pulse width modulation, and wherein the decoder is to determine a duty cycle of the modulated RTC signal based on the shared clock signal.
18. The circuit of claim 16 , wherein the clock information indicates a temperature associated with a crystal oscillator that generates the shared clock signal, and wherein the decoder is further to adjust the shared clock signal based on the temperature.
19. The circuit of claim 16 , wherein the modulated RTC signal encodes multiple bits per cycle of the modulated RTC signal.
A circuit for a real-time clock (RTC) system includes a modulation mechanism that encodes multiple bits of data per cycle of the RTC signal. The RTC signal is modulated to carry additional information beyond standard timekeeping, allowing for efficient data transmission within the existing clock signal. This approach leverages the periodic nature of the RTC signal to embed digital data, enabling higher data density without requiring additional signal lines or significant power overhead. The modulation technique may involve varying signal characteristics such as amplitude, frequency, or phase to represent different bit patterns. By encoding multiple bits per cycle, the system improves data throughput while maintaining compatibility with conventional RTC hardware. This method is particularly useful in embedded systems where bandwidth and power efficiency are critical, allowing for simultaneous timekeeping and data communication over a single signal path. The circuit may include a demodulation component to extract the encoded data from the modulated RTC signal, ensuring accurate retrieval of the transmitted information. This technique enhances the functionality of RTC systems by integrating data communication capabilities without compromising timekeeping accuracy or increasing system complexity.
20. An apparatus comprising: means to receive clock information associated with a shared clock signal that is to be used by a plurality of circuit dies, wherein the clock information includes temperature information; means to modulate a real time clock (RTC) signal with the clock information by adjusting a timing of a falling edge of the RTC signal, wherein the RTC signal has a frequency that is less than a frequency of the shared clock signal, wherein the means to modulate the RTC signal includes: means to provide the modulated RTC signal with a first pulse width to indicate a start of a message; means to provide the modulated RTC signal with a second pulse width to indicate an end of a message; and means to maintain the modulated RTC signal with the second pulse width after the end of the message and until a start of a next message; and means to distribute the modulated RTC signal to the plurality of circuit dies.
21. The apparatus of claim 20 , wherein the means to modulate the RTC signal includes: means to provide the modulated RTC signal with a first duty cycle over a first cycle to indicate that a first bit encoded by the modulated RTC signal is a first logic value; and means to provide the modulated RTC signal with a second duty cycle over a second cycle to indicate that a second bit encoded by the modulated RTC signal is a second logic value, wherein the second duty cycle is different than the first duty cycle and the second logic value is different than the first logic value.
22. The apparatus of claim 20 , wherein the modulated RTC signal is to encode a plurality of bits per cycle of the modulated RTC signal based on a duty cycle of the modulated RTC signal.
This invention relates to a system for encoding digital data using a modulated real-time clock (RTC) signal. The problem addressed is the need for efficient data transmission in systems where bandwidth is limited, such as in low-power or embedded devices. Traditional RTC signals typically transmit one bit per cycle, limiting data throughput. The invention improves this by encoding multiple bits per cycle through duty cycle modulation, allowing higher data rates without increasing clock frequency. The apparatus includes a signal generator that produces a modulated RTC signal, where the duty cycle of the signal encodes multiple bits. For example, different duty cycles (e.g., 25%, 50%, 75%) can represent different bit patterns, such as 00, 01, 10, or 11. A decoder interprets these duty cycles to extract the encoded data. The system may also include a synchronization mechanism to align the transmitter and receiver, ensuring accurate bit recovery. The modulation scheme can be adjusted dynamically to optimize for power efficiency or data rate, depending on system requirements. This approach enables higher data throughput in constrained environments while maintaining compatibility with existing RTC-based communication protocols.
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March 9, 2021
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