Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A method for regulating peak to average power ratio, PAR, of an output signal of a crest factor reduction, CFR, circuit, the method comprising: receiving an input signal at an input of the CFR circuit; determining a magnitude of the input signal; clipping the input signal magnitude to a target level to produce an error signal by comparing the input signal magnitude to a threshold in a comparator; filtering the error signal to produce a processed error signal, the filter providing a bandpass filter frequency response; and regulating the PAR of the output signal by scaling the processed error signal by an error scaling factor to achieve a target signal to noise ratio, SNR, for the output signal corresponding to a target error vector magnitude, EVM.
This invention relates to power amplification systems, specifically addressing the challenge of regulating the peak-to-average power ratio (PAR) in crest factor reduction (CFR) circuits to improve signal quality. High PAR in communication signals can lead to inefficient power amplification and degraded performance. The method involves receiving an input signal at a CFR circuit and determining its magnitude. The input signal magnitude is then clipped to a predefined target level by comparing it to a threshold in a comparator, generating an error signal. This error signal is filtered using a bandpass filter to produce a processed error signal. The processed error signal is scaled by an error scaling factor to regulate the PAR of the output signal, ensuring a target signal-to-noise ratio (SNR) and error vector magnitude (EVM). The scaling factor adjusts the error signal to maintain optimal signal quality while minimizing distortion. The bandpass filter ensures that only relevant frequency components of the error signal are used for PAR regulation, enhancing system efficiency and performance. This approach enables precise control of PAR, improving amplifier linearity and reducing power consumption in communication systems.
2. The method of claim 1 , wherein the error scaling factor is a function of a level of the input signal, the target SNR and a level of the processed error signal.
3. The method of claim 2 , wherein the error scaling factor is given in dB by: error scaling factor=a root mean square, RMS, value of the input signal magnitude− the target SNR in dB− an RMS value of the processed error signal.
This invention relates to signal processing techniques for optimizing error correction in communication systems. The problem addressed is the need to dynamically adjust error scaling factors to improve signal quality while maintaining efficient processing. Traditional methods often fail to adaptively balance error correction with computational efficiency, leading to suboptimal performance. The invention provides a method for calculating an error scaling factor in decibels (dB) to enhance signal processing accuracy. The error scaling factor is determined by subtracting the target signal-to-noise ratio (SNR) in dB and the root mean square (RMS) value of the processed error signal from the RMS value of the input signal magnitude. This calculation ensures that the error correction process is dynamically adjusted based on real-time signal characteristics, improving overall system performance. The method involves processing an input signal to generate a processed error signal, which is then used to refine the error scaling factor. By continuously updating the scaling factor using the RMS values of both the input signal and the processed error signal, the system achieves adaptive error correction that responds to varying signal conditions. This approach optimizes the balance between error reduction and computational overhead, making it suitable for applications requiring high precision and efficiency in signal processing.
4. The method of claim 1 , wherein the clipping, filtering and scaling occur continuously during operation of the CFR circuit to provide a continuously regulated output signal with a single iteration of the clipping and filtering.
5. The method of claim 1 , wherein the target EVM is based on a transceiver link budget.
A method for optimizing error vector magnitude (EVM) in wireless communication systems addresses the challenge of maintaining signal quality under varying link conditions. The technique involves dynamically adjusting EVM based on a transceiver link budget, which accounts for factors like path loss, interference, and noise. By correlating EVM with the link budget, the system ensures reliable communication while minimizing power consumption and spectral efficiency trade-offs. The method includes determining the link budget by analyzing signal strength, interference levels, and receiver sensitivity. Based on this analysis, the EVM threshold is dynamically adjusted to balance performance and resource utilization. This approach prevents excessive power usage in strong signal conditions while maintaining signal integrity in weak signal scenarios. The technique is particularly useful in wireless networks where adaptive modulation and coding schemes are employed to optimize throughput and coverage. By integrating link budget considerations into EVM management, the method enhances system robustness and efficiency in diverse operating environments.
6. The method of claim 1 , wherein the regulating comprises reducing the PAR of the output signal using the processed error signal scaled to achieve the target SNR for the output signal.
7. The method of claim 1 , wherein the regulating comprises subtracting the processed error signal scaled from a delayed version of the input signal to produce the output signal.
8. The method of claim 1 , wherein the target EVM is selected based on the target PAR reduction and a transceiver link budget.
9. The method of claim 8 , wherein a lower target EVM is chosen to achieve a lower target PAR reduction.
This invention relates to wireless communication systems, specifically methods for reducing peak-to-average power ratio (PAR) in transmitted signals while maintaining acceptable error vector magnitude (EVM) performance. High PAR in wireless signals can lead to inefficiencies in power amplifiers, increasing power consumption and reducing battery life in mobile devices. The invention addresses this by dynamically adjusting the target EVM to achieve a desired PAR reduction. By selecting a lower target EVM, the system can more aggressively reduce PAR, improving power amplifier efficiency without compromising signal quality beyond acceptable limits. The method involves monitoring signal quality metrics, such as EVM, and adjusting the target EVM value based on the desired PAR reduction level. This adaptive approach ensures that PAR is minimized while maintaining reliable communication performance. The technique is particularly useful in modern wireless standards where both power efficiency and signal integrity are critical. The invention may be implemented in transmitters, base stations, or mobile devices to optimize power usage and extend operational time.
10. The method of claim 1 , wherein the clipping, filtering and scaling occur iteratively during operation of the CFR circuit, each iteration using a respective error scaling factor where the respective error scaling factors collectively achieve the target SNR for the output signal corresponding to the target EVM.
11. A crest factor reduction, CFR, circuit configured to regulate a peak to average power ratio, PAR, of an output signal of the CFR circuit the circuit comprising: a magnitude determiner configured to determine a magnitude of an input signal; a clipping circuit configured to clip the input signal to a target level to produce an error signal by comparing the input signal magnitude to a threshold and capturing a portion of the magnitude exceeding the threshold; a filter configured to filter the error signal to produce a processed error signal, the filtering providing a band pass filter frequency response; a gain circuit configured to scale the processed error signal by an error scaling factor to achieve a target signal to noise ratio, SNR, for the output signal based on a target error vector magnitude, EVM, the scaling functioning to regulate the output signal of the CFR circuit.
12. The circuit of claim 11 , wherein the error scaling factor is a function of a level of the input signal, the target SNR, and a level of the processed error signal.
13. The circuit of claim 12 , wherein the error scaling factor is given in dB by: error scaling factor=a root mean square, RMS, value of the input signal magnitude− the target SNR in dB− an RMS value of the processed error signal.
14. The circuit of claim 11 , wherein the clipping, filtering and scaling occur continuously during operation of the CFR circuit to provide a continuously regulated output with a single iteration of the clipping and filtering.
15. The circuit of claim 11 , wherein the target EVM is based on a transceiver link budget.
A wireless communication circuit includes a transmitter and receiver configured to operate in a high-frequency band, such as millimeter-wave (mmWave) frequencies, where signal propagation challenges like path loss and interference are significant. The circuit dynamically adjusts transmission parameters to maintain signal quality under varying channel conditions. A key feature is the use of error vector magnitude (EVM) as a performance metric, which measures the deviation of transmitted signals from ideal modulation points. The circuit includes a feedback loop that monitors EVM and adjusts power, modulation scheme, or coding rate to optimize performance. Additionally, the circuit incorporates a target EVM value derived from a transceiver link budget, which accounts for factors like path loss, noise, and interference to ensure reliable communication. The link budget-based target EVM allows the system to balance power efficiency and data throughput while meeting quality-of-service requirements. This approach is particularly useful in mmWave systems where signal integrity is critical due to high attenuation and susceptibility to environmental factors. The circuit may also include adaptive beamforming to further enhance signal quality.
16. The circuit of claim 11 , wherein the regulating comprises reducing the PAR of the output signal using the processed error signal scaled to achieve the target SNR for the output signal.
17. The circuit of claim 11 , wherein the regulating comprises subtracting the processed error signal scaled from a delayed version of the input signal to produce the output signal.
18. The circuit of claim 11 , wherein the target EVM is selected based on the target PAR reduction and a transceiver link budget.
A wireless communication circuit includes a power amplifier (PA) with a digital pre-distortion (DPD) system that adjusts the PA's output to reduce peak-to-average ratio (PAR) while maintaining error vector magnitude (EVM) within acceptable limits. The circuit dynamically selects a target EVM based on the desired PAR reduction and the transceiver's link budget. The link budget accounts for factors like signal attenuation, noise, and interference to ensure reliable communication. By balancing PAR reduction with EVM constraints, the circuit optimizes power efficiency and signal integrity. The DPD system uses adaptive algorithms to compensate for PA nonlinearities, improving linearity and reducing spectral emissions. The circuit may also include feedback mechanisms to monitor performance and adjust parameters in real-time. This approach enhances spectral efficiency and power efficiency in wireless transmitters, particularly in high-data-rate applications where both PAR and EVM must be carefully managed. The solution is applicable to modern wireless standards requiring strict compliance with spectral masks and EVM thresholds.
19. The circuit of claim 18 , wherein a lower target EVM is chosen to achieve a lower target PAR reduction.
20. The circuit of claim 11 , wherein the clipping, filtering and scaling occur iteratively during operation of the CFR circuit, each iteration using a respective error scaling factor where the respective error scaling factors collectively achieve the target SNR for the output signal corresponding to the target EVM.
21. An error scaling circuit, comprising: an input signal level determiner configured to determine a level of a input signal power; a processed error signal level determiner configured to determine a level of a processed error signal power, the first processed error signal being obtained from a signal clipped to a target level; a signal to noise ratio, SNR, memory configured to store an SNR level, the SNR level being based on a target error vector magnitude, EVM; and an error scaling factor calculator configured to calculate an error scaling factor to scale the first processed error signal to achieve the SNR level.
22. The error scaling circuit of claim 21 , wherein the error scaling factor is a function of the target SNR level, a level of the input signal and a level of the processed error signal.
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March 9, 2021
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