Pattern Centric Process Control

1. A system, comprising: a processor configured to: decompose a layout of a semiconductor chip into a plurality of intended circuit layout patterns; determine, for the plurality of intended circuit layout patterns, a corresponding plurality of sets of fabrication risk assessments corresponding to respective ones of a plurality of sources, wherein determining a set of fabrication risk assessments for a given intended circuit layout pattern in the plurality comprises determining fabrication risk assessments based at least in part on at least two or more of: simulation of the given intended circuit layout pattern, statistical analysis of the given intended circuit layout pattern, and evaluation of empirical data associated with one or more printed circuit layout patterns; for an intended circuit layout pattern that does not have a fabrication risk assessment based on empirical data of a corresponding printed circuit layout pattern: obtain fabrication risk assessments for a subset of the plurality of intended circuit layout patterns, wherein the fabrication risk assessments for the subset of the plurality of intended circuit layout patterns are based at least in part on empirical data associated with printed circuit layout patterns corresponding to the subset of the plurality of intended circuit layout patterns; predict, based at least in part on the obtained fabrication risk assessments for the subset of the plurality of intended circuit layout patterns, a fabrication risk assessment for the intended circuit layout pattern; and assign, to the intended circuit layout pattern, the fabrication risk assessment predicted based at least on the obtained fabrication risk assessments for the subset of the plurality of intended circuit layout patterns; apply a scoring formula based at least in part on the sets of fabrication risk assessments to obtain a plurality of overall fabrication risk assessments for respective ones of the plurality of intended circuit layout patterns; rank the plurality of intended circuit layout patterns based on their fabrication risk assessments, the corresponding overall fabrication risk assessments, or both; and output at least a portion of ranking information to facilitate influence or control over a semiconductor fabrication process; and a memory coupled to the processor and configured to provide the processor with instructions.

2. The system of claim 1 , wherein determining a fabrication risk assessment for the given intended circuit layout pattern based at least in part on statistical analysis of the given intended circuit layout pattern comprises: generating a set of design signatures for the given intended circuit layout pattern; determining the fabrication risk assessment for the given intended circuit layout pattern based at least in part on the generated set of design signatures; and assigning, to the given intended circuit layout pattern, the fabrication risk assessment determined based at least in part on the generated set of design signatures.

3. The system of claim 2 wherein the set of design signatures generated for the given intended circuit layout pattern comprises statistical summaries of one or more of pattern complexity, pattern directionality, pattern density, and pattern homogeneity.

4. The system of claim 2 wherein the set of design signatures are generated from the layout of the semiconductor chip.

5. The system of claim 1 , wherein determining a fabrication risk assessment for the given intended circuit layout pattern based at least in part on simulation of the given intended circuit layout pattern comprises: performing optical proximity correction (OPC) simulation on the given intended circuit layout pattern; determining the fabrication risk assessment for the given intended circuit layout pattern based at least in part on a result of the OPC simulation performed on the given intended circuit layout pattern; and assigning, to the given intended circuit layout pattern, the fabrication risk assessment determined based at least in part on the result of the OPC simulation performed on the given intended circuit layout pattern.

6. The system of claim 1 , wherein the processor is further configured to adjust an optical proximity correction model based at last in part on the ranking of the plurality of intended circuit layout patterns of the semiconductor chip.

7. The system of claim 1 , wherein the processor is further configured to: perform optical proximity correction (OPC) simulation on the layout of the semiconductor chip; and determine fabrication risk assessments for at least some of the intended circuit layout patterns in the plurality at least in part by cross-referencing an optical proximity correction (OPC) verification report with the at least some of the intended circuit layout patterns.

8. The system of claim 1 , wherein determining a fabrication risk assessment for the given intended circuit layout pattern based at least in part on evaluation of empirical data associated with one or more printed circuit layout patterns comprises: obtaining empirical data associated with a printed circuit layout pattern; determining that the printed circuit layout pattern corresponds to the given intended circuit layout pattern; determining the fabrication risk assessment for the given intended circuit layout pattern based at least in part on the empirical data associated with the printed circuit layout pattern determined to correspond to the given intended circuit layout pattern; and assigning, to the given intended circuit layout pattern, the fabrication risk assessment determined based at least in part on the empirical data associated with the printed circuit layout pattern determined to correspond to the given intended circuit layout pattern.

9. The system of claim 1 , wherein the predicting of the fabrication risk assessment is based at least in part on machine learning.

10. The system of claim 9 , wherein the predicting of the fabrication risk assessment is performed using at least one of support vector machines (SVM), K-nearest neighbor, convolutional neural networks, and deep learning networks.

11. The system of claim 9 , wherein the predicting of the fabrication risk assessment includes: deriving a feature vector corresponding to the intended circuit layout pattern that does not have a fabrication risk assessment based on empirical data of a corresponding printed circuit layout pattern; and comparing the derived feature vector with cluster(s) of good-pattern feature vectors and cluster(s) of bad-pattern feature vectors to determine whether the derived feature vector is to be clustered in one of the cluster(s) of good-pattern feature vectors or one of the cluster(s) of bad-pattern feature vectors.

12. The system of claim 11 , wherein the clusters of good-pattern and bad-pattern feature vectors are generated at least in part by: accessing a set of known good intended circuit layout patterns and a set of known bad intended circuit layout patterns obtained from empirical data of corresponding printed circuit layout patterns; starting with an initial set of feature parameters, generating the cluster of good-pattern feature vectors from the set of known good intended circuit layout patterns and the cluster of bad-pattern feature vectors from the set of known bad intended circuit layout patterns, based at least in part on the initial set of feature parameters; determining an amount of overlap between the cluster(s) of good-pattern feature vectors and the cluster(s) of bad-pattern feature vectors; and in response to a determination that the amount of overlap exceeds a resolution threshold, adjusting the initial set of feature parameters, and iteratively regenerating the cluster(s) of good-pattern feature vectors and the cluster(s) of bad-pattern feature vectors, based on the adjusted set of feature parameters.

13. The system of claim 1 , wherein the processor is configured to output the at least portion of the ranking information to be displayed.

14. The system of claim 1 , wherein the processor is configured to output the at least portion of the ranking information to one or more of a design verification tool, a metrology tool, an inspection tool, and an imaging tool.

15. The system of claim 1 , wherein each source is associated with a corresponding reliability.

16. The system of claim 1 , wherein each source is associated with a corresponding coverage indicating what percentage of the plurality of intended circuit layout patterns that are covered by the source.

17. The system of claim 1 , wherein the processor is further configured to rank each source according to at least one of a corresponding reliability and coverage.

18. The system of claim 1 , wherein the semiconductor chip comprises a first semiconductor chip, and further comprises generating a yield estimation or risk assessment for a second semiconductor chip based at least in part on the ranking of the plurality of intended circuit layout patterns of the first semiconductor chip.

19. A method, comprising: decomposing a layout of a semiconductor chip into a plurality of intended circuit layout patterns; determining, for the plurality of intended circuit layout patterns, a corresponding plurality of sets of fabrication risk assessments corresponding to respective ones of a plurality of sources, wherein determining a set of fabrication risk assessments for a given intended circuit layout pattern in the plurality comprises determining fabrication risk assessments based at least in part on at least two or more of: simulation of a given intended circuit layout pattern, statistical analysis of the given intended circuit layout pattern, and evaluation of empirical data associated with one or more printed circuit layout patterns; for an intended circuit layout pattern that does not have a fabrication risk assessment based on empirical data of a corresponding printed circuit layout pattern: obtain fabrication risk assessments for a subset of the plurality of intended circuit layout patterns, wherein the fabrication risk assessments for the subset of the plurality of intended circuit layout patterns are based at least in part on empirical data associated with printed circuit layout patterns corresponding to the subset of the plurality of intended circuit layout patterns; predict, based at least in part on the obtained fabrication risk assessments for the subset of the plurality of intended circuit layout patterns, a fabrication risk assessment for the intended circuit layout pattern; and assign, to the intended circuit layout pattern, the fabrication risk assessment predicted based at least on the obtained fabrication risk assessments for the subset of the plurality of intended circuit layout patterns; applying a scoring formula based at least in part on the sets of fabrication risk assessments to obtain a plurality of overall fabrication risk assessments for respective ones of the plurality of intended circuit layout patterns; ranking the plurality of intended circuit layout patterns based on their fabrication risk assessments, the corresponding overall fabrication risk assessments, or both; and outputting at least a portion of ranking information to facilitate influence or control over a semiconductor fabrication process.

20. A computer program product embodied in a non-transitory computer readable storage medium and comprising computer instructions for: decomposing a layout of a semiconductor chip into a plurality of intended circuit layout patterns; determining, for the plurality of intended circuit layout patterns, a corresponding plurality of sets of fabrication risk assessments corresponding to respective ones of a plurality of sources, wherein determining a set of fabrication risk assessments for a given intended circuit layout pattern in the plurality comprises determining fabrication risk assessments based at least in part on at least two or more of: simulation of the given intended circuit layout pattern, statistical analysis of the given intended circuit layout pattern, and evaluation of empirical data associated with a printed circuit layout pattern; for an intended circuit layout pattern that does not have a fabrication risk assessment based on empirical data of a corresponding printed circuit layout pattern: obtain fabrication risk assessments for a subset of the plurality of intended circuit layout patterns, wherein the fabrication risk assessments for the subset of the plurality of intended circuit layout patterns are based at least in part on empirical data associated with printed circuit layout patterns corresponding to the subset of the plurality of intended circuit layout patterns; predict, based at least in part on the obtained fabrication risk assessments for the subset of the plurality of intended circuit layout patterns, a fabrication risk assessment for the intended circuit layout pattern; and assign, to the intended circuit layout pattern, the fabrication risk assessment predicted based at least on the obtained fabrication risk assessments for the subset of the plurality of intended circuit layout patterns; applying a scoring formula based at least in part on the sets of fabrication risk assessments to obtain a plurality of overall fabrication risk assessments for respective ones of the plurality of intended circuit layout patterns; ranking the plurality of intended circuit layout patterns based on their fabrication risk assessments, the corresponding overall fabrication risk assessments, or both; and outputting at least a portion of ranking information to facilitate influence or control over a semiconductor fabrication process.