10999048

Superior Timing Synchronization Using High-Order Tracking Loops

PublishedMay 4, 2021
Assigneenot available in USPTO data we have
Technical Abstract

Patent Claims
20 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A symbol-timing tracking system for a receiver, comprising: an analog-to-digital converter (ADC) configured to generate a digital signal by sampling an analog signal received at the receiver; an interpolator configured to adjust a sampling rate of the digital signal; a receive filter configured to apply a receive filtering function to the digital signal to generate a filtered signal; a timing error detector (TED) configured to generate a timing error signal from the filtered signal; a loop filter of third order or higher, the loop filter configured to filter the timing error signal to remove self-noise present in the timing error signal and generate a filtered timing error signal; and a numerically controlled oscillator (NCO) configured to control timing data based on the filtered timing error signal and provide the timing data to the interpolator, wherein the interpolator is configured to correct for timing of the digital signal based on the timing data, and adjust the sampling rate of the digital signal based on the timing data.

2

2. The symbol-timing tracking system of claim 1 , wherein the TED is nonlinear and generates the self-noise due to its nonlinearity, wherein the loop filter is configured to filter out the self-noise generated by the TED due to its nonlinearity.

3

3. The symbol-timing tracking system of claim 2 , wherein the TED is not data-aided, wherein a carrier phase offset of the analog signal is unknown by the TED, and wherein the analog signal is shifted in time by an amount unknown by the TED.

4

4. The symbol-timing tracking system of claim 1 , wherein the loop filter is configured to track higher order dynamics of a timing signal.

5

5. The symbol-timing tracking system of claim 4 , wherein the higher order dynamics comprise a clock timing-ramp or a clock frequency-ramp.

6

6. The symbol-timing tracking system of claim 1 , wherein the analog signal comprises complex-valued symbols drawn from a 32 APSK constellation, a 64 APSK constellation, a 128 APSK constellation, or a 256 APSK constellation.

7

7. The symbol-timing tracking system of claim 1 , wherein the analog signal is shaped by a root raised-cosine (RRC) transmit filter, wherein the receive filter is matched to the RRC transmit filter.

8

8. The symbol-timing tracking system of claim 6 , wherein the analog signal is shaped by a root raised-cosine (RRC) transmit filter, wherein the receive filter is matched to the RRC transmit filter.

9

9. The symbol-timing tracking system of claim 1 , wherein the loop filter is an infinite impulse response (IIR) filter.

10

10. The symbol-timing tracking system of claim 9 , wherein an output v[n] of the IIR filter is given by: v ⁡ [ n ] = ∑ k = 0 N β ⁢ β k · u ⁡ [ n - k ] - ∑ k = 1 N α ⁢ α k · v ⁡ [ n - k ] , where N α and N β are orders of feedback and feedforward filtering operations of the IIR filter, respectively, α k and β k are constants, and u[n] is an input of the IIR filter.

11

11. The symbol-timing tracking system of claim 9 , wherein the IIR filter is configured with a loop of third-order or fourth-order.

12

12. A method, comprising: sampling an analog signal received at a receiver to generate a digital signal; adjusting, using an interpolator, a sampling rate of the digital signal; applying a receive filtering function to the digital signal to generate a filtered signal; generating, using a timing error detector (TED), a timing error signal from the filtered signal; filtering, using a loop filter of third order or higher, the timing error signal to remove self-noise present in the timing error signal and generate a filtered timing error signal; and controlling, using a numerically controlled oscillator (NCO), timing data based on the filtered timing error signal; and providing the timing data to the interpolator, wherein the interpolator is configured to correct for timing of the digital signal based on the timing data, and adjust the sampling rate of the digital signal based on the timing data.

13

13. The method of claim 12 , wherein the TED is nonlinear and generates the self-noise due to its nonlinearity, wherein filtering the timing error signal comprises filtering the self-noise generated by the TED due to its nonlinearity.

14

14. The method of claim 13 , wherein the TED is not data-aided, wherein a carrier phase offset of the analog signal is unknown by the TED, and wherein the analog signal is shifted in time by an amount unknown by the TED.

15

15. The method of claim 12 , wherein the loop filter is configured to track higher order dynamics of a timing signal, wherein the higher order dynamics comprise a clock timing-ramp or a clock frequency-ramp.

16

16. The method of claim 12 , wherein the analog signal comprises complex-valued symbols drawn from a 32 APSK constellation, a 64 APSK constellation, a 128 APSK constellation, or a 256 APSK constellation, wherein the analog signal is shaped by a root raised-cosine (RRC) transmit filter, wherein the receive filter is matched to the RRC transmit filter.

17

17. The method of claim 12 , wherein the loop filter is an infinite impulse response (IIR) filter, wherein an output v[n] of the IIR filter is given by: v ⁡ [ n ] = ∑ k = 0 N β ⁢ β k · u ⁡ [ n - k ] - ∑ k = 1 N α ⁢ α k · v ⁡ [ n - k ] , where N α and N β are orders of feedback and feedforward filtering operations of the IIR filter, respectively, α k and β k are constants, and u[n] is an input of the IIR filter.

18

18. A receiver, comprising: circuitry configured to receive an analog signal from a wireless communication network; and a symbol-timing tracking system, comprising: an analog-to-digital converter (ADC) configured to generate a digital signal by sampling the analog signal; an interpolator configured to adjust a sampling rate of the digital signal; a receive filter configured to apply a receive filtering function to the digital signal to generate a filtered signal; a timing error detector (TED) configured to generate a timing error signal from the filtered signal; a loop filter of third order or higher, the loop filter configured to filter the timing error signal to remove self-noise present in the timing error signal and generate a filtered timing error signal; and a numerically controlled oscillator (NCO) configured to control timing data based on the filtered timing error signal and provide the timing data to the interpolator, wherein the interpolator is configured to correct for timing of the digital signal based on the timing data, and adjust the sampling rate of the digital signal based on the timing data.

19

19. The receiver of claim 18 , wherein the TED is nonlinear and generates the self-noise due to its nonlinearity, wherein the loop filter is configured to filter out self-noise generated by the TED due to its nonlinearity.

20

20. The receiver of claim 18 , wherein the wireless communication network comprises a satellite communications network, wherein the circuitry is configured to receive the analog signal from a satellite transponder of the satellite communications network.

Patent Metadata

Filing Date

Unknown

Publication Date

May 4, 2021

Inventors

Bassel F. Beidas

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Cite as: Patentable. “SUPERIOR TIMING SYNCHRONIZATION USING HIGH-ORDER TRACKING LOOPS” (10999048). https://patentable.app/patents/10999048

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