Hard Error Simulation and Usage Thereof

1. A computer-implemented method comprising: obtaining a design of a circuit, wherein the circuit comprises nodes which are assigned values during execution, wherein the circuit comprises one or more monitoring signals for identifying errors and one or more critical nodes; obtaining a first hard error fault on a first node, wherein the first hard error fault is potentially capable of causing a wrong value to reach the one or more critical nodes; obtaining a second hard error fault on a second node, wherein the second hard error fault is potentially capable of causing a wrong value to reach the one or more critical nodes; determining, by a processor, a first hard-error test coverage for the first hard error fault, and a second hard-error test coverage for second hard error fault, wherein the first hard-error test coverage is indicative of whether or not the one or more monitoring signals identifies the first hard error fault during an execution of a first test, wherein the second hard-error test coverage is indicative of whether or not the one or more monitoring signals identifies the second hard error fault during an execution of a second test; and wherein said determining comprises: simulating the execution of the circuit together with a hard error fault and noting whether or not any one or more of the one or more monitoring signals has detected the hard error fault, wherein the hard error fault is selected from the first hard error and the second hard error respectively; and outputting a first indication of the first hard-error test coverage and a second indication of the second hard-error test coverage, wherein the first indication indicates susceptibility of the design to the first hard error fault given the first test, wherein the second indication indicates susceptibility of the design to the second hard error fault given the second test.

2. The computer-implemented method of claim 1 , wherein said determining is performed with respect to a plurality of nodes comprised in the circuit, whereby test coverage is determined for each node of the plurality of nodes, wherein said outputting comprises outputting an associated list of the plurality of the nodes and associated coverage values of the first hard error fault and the second hard error fault on the plurality of nodes.

3. The computer-implemented method of claim 2 , wherein said outputting comprises outputting an aggregate coverage value, wherein the aggregate coverage value is a ratio of executions in which hard error faults were detected out of all possible executions.

4. The computer-implemented method of claim 1 , wherein said simulating execution comprises: determining a modified design simulating the hard error fault, wherein the modified design is configured to set a value of the first node or the second node, respectively to the hard error fault, to a constant value in each cycle.

5. The computer-implemented method of claim 1 , wherein said simulating execution comprises: determining a modified design simulating the hard error fault, wherein the modified design is configured to set a value of the first node or the second node, respectively to the hard error fault, to a random value in each cycle that is not influenced by input signals to the first node or the second node, respectively to the hard error fault.

6. The computer-implemented method of claim 1 , wherein said simulating execution comprises: determining a modified design simulating the hard error fault, wherein the modified design is configured to set a value of the first node or the second node, respectively to the hard error fault, to an X value in each cycle, representing an unknown value.

7. The computer-implemented method of claim 1 , wherein at least one of the one or more monitoring signals is part of a Built-In Self Test (BIST) or part of a lock-step or Triple Modular Redundancy (TMR) construct.

8. The computer-implemented method of claim 1 , further comprising: obtaining a recording of a reference execution of the circuit, wherein the recording comprises recorded values of the nodes in a plurality of cycles; and wherein said simulating the execution of the circuit is performed using the recorded values of the reference execution.

9. A computer program product comprising a computer readable storage medium retaining program instructions, which program instructions when read by a processor, cause the processor to perform: obtaining a design of a circuit, wherein the circuit comprises nodes which are assigned values during execution, wherein the circuit comprises one or more monitoring signals for identifying errors and one or more critical nodes; obtaining a first hard error fault on a first node, wherein the first hard error fault is potentially capable of causing a wrong value to reach the one or more critical nodes; obtaining a second hard error fault on a second node, wherein the second hard error fault is potentially capable of causing a wrong value to reach the one or more critical nodes; determining, by the processor, a first hard-error test coverage for the first hard error fault, and a second hard-error test coverage for the second hard error fault, wherein the first hard-error test coverage is indicative of whether or not the one or more monitoring signals identifies the first hard error fault during an execution of a first test, wherein the second hard-error test coverage is indicative of whether or not the one or more monitoring signals identifies the second hard error fault during an execution of a second test; and wherein said determining comprises: simulating the execution of the circuit together with a hard error fault and noting whether or not any one or more of the one or more monitoring signals has detected the hard error fault, wherein the hard error fault is selected from the first hard error and the second hard error respectively; and outputting a first indication of the first hard-error test coverage and a second indication of the second hard-error test coverage, wherein the first indication indicates susceptibility of the design to the first hard error fault given the first test, wherein the second indication indicates susceptibility of the design to the second hard error fault given the second test.

10. The computer program product of claim 9 , wherein said determining is performed with respect to a plurality of nodes comprised in the circuit, whereby test coverage is determined for each node of the plurality of nodes, wherein said outputting comprises outputting an associated list of the plurality of the nodes and associated coverage values of the first hard error fault and the second hard error fault on the plurality of nodes.

11. The computer program product of claim 10 , wherein said outputting comprises outputting an aggregate coverage value, wherein the aggregate coverage value is a ratio of executions in which hard error faults were detected out of all possible executions.

12. The computer program product of claim 9 , wherein said program instructions, when read by the processor, cause the processor to perform: obtaining a recording of a reference execution of the circuit, wherein the recording comprises recorded values of the nodes in a plurality of cycles; and wherein said simulating the execution of the circuit is performed using the recorded values of the reference execution.