Gate Driver on Array Circuit

1. A Gate Driver on Array (GOA) circuit for a display panel comprising a plurality of cascaded GOA units, wherein the GOA units comprises a first dummy GOA unit and/or a second dummy GOA unit not connecting scan lines of the display panel's active area; the GOA units further comprises a plurality of normal GOA units connecting scan lines of the active area; the normal GOA units are cascaded into a chain of normal GOA units; the first dummy GOA unit is cascaded to a first normal GOA unit of the chain of normal GOA units and/or the second dummy GOA unit is cascaded to a last normal GOA unit of the chain of normal GOA units; a start signal of the display panel's vertical scanning as a cascaded signal is input into the first dummy GOA unit and/or the start signal as a cascaded signal is input into the second dummy GOA unit; a GOA unit at a nth (n is a natural number) stage of the plurality of cascaded GOA units comprises a pull-up control module, a pull-up module, a pull-down control module, a pull-down module, a general control module, and a reset module; the pull-up control module receives the cascaded signal from a GOA unit at a previous stage and/or at a next stage, and controls the pull-up module to pull up a voltage level at the GOA unit's scanning signal output terminal; the pull-down control module controls the pull-down module to pull down the voltage level at the GOA unit's scanning signal output terminal; the general control module controls the voltage level at the GOA unit's scanning signal output terminal; the reset module resets the voltage level at the GOA unit's scanning signal output terminal; and the pull-down control module comprises: a third TFT having the gate connected to a forward scanning signal, the source connected to a (n+1)th-stage clock signal, and the drain connected to the gate of an eighth TFT; a fourth TFT having the gate connected to a backward scanning signal, the source connected to a (n−1)th-stage clock signal, and the drain connected to the gate of the eighth TFT; a sixth TFT having the gate connected to a first junction, the source connected to a second junction, and the drain connected to a low-level signal; the eighth TFT having the source connected to the second junction, and the drain connected to a high-level signal; and a twelfth TFT having the gate connected to a general control signal, the source connected to the second junction, and the drain connected to the low-level signal.

2. The GOA circuit according to claim 1 , wherein the pull-up control module comprises a first thin film transistor (TFT) having the gate connected to the scanning signal output terminal of a GOA unit at a (n−2)th stage, the source connected to a forward scanning signal, and the drain connected to a first junction; a second TFT having the gate connected to the scanning signal output terminal of a GOA unit at a (n+2)th stage, the source connected to a backward scanning signal, and the drain connected to the first junction; a fifth TFT having the gate connected to a second junction, the source connected to the first junction, and the drain connected to a low-level signal; and a seventh TFT having the gate connected to a high-level signal, the source connected to the first junction, and the drain, as the pull-up control module's output terminal, connected to the pull-up module.

3. The GOA circuit according to claim 1 , wherein the pull-up module comprises a ninth TFT having the gate connected to an output terminal of the pull-up control module, the source connected to a nth-stage clock signal, and the drain connected to the scanning signal output terminal.

4. The GOA circuit according to claim 1 , wherein the pull-down module comprises a tenth TFT having the gate connected to a second junction, the source connected to the scanning signal output terminal, and the drain connected to a low-level signal.

5. The GOA circuit according to claim 1 , wherein the general control module comprises an eleventh TFT having the gate connected to a general control signal, the source connected to the general control signal, and the drain connected to scanning signal output terminal.

6. The GOA circuit according to claim 1 , wherein the reset module comprises a thirteenth TFT having the gate connected to a reset signal, the source connected to the reset signal, and the drain connected to a second junction.

7. The GOA circuit according to claim 1 , wherein the GOA unit at the nth stage further comprises a first capacitor having its two terminals connected to a first junction and a low-level signal, respectively.

8. The GOA circuit according to claim 1 , where the GOA unit at the nth stage further comprises a second capacitor having its two terminals connected to a second junction and a low-level signal, respectively.