Multi-Patterning Graph Reduction and Checking Flow Method

1. A method of generating a plurality of photomasks for a photolithographic process, comprising: generating a circuit graph representative of a circuit layout having a plurality of conductive lines, wherein the graph comprises a plurality of vertices and a plurality of edges, wherein each of the plurality of vertices is representative of a corresponding one of the plurality of conductive lines, and wherein each of the plurality of edges is representative of a spacing between the conductive lines less than an acceptable minimum distance; performing at least one K n+1 graph reduction of the circuit graph to generate a reduced circuit graph; performing an n-pattern conflict check on the reduced circuit graph; and generating a plurality of photomasks based on a result of the n-pattern conflict check.

2. The method of claim 1 , comprising removing from the circuit graph a second set of vertices selected from the plurality of vertices, wherein each of the vertices in the second set of vertices has less than n edge connections.

3. The method of claim 1 , comprising recording each of the plurality of vertices and each of the plurality of edges prior to performing the at least one K n+1 graph reduction.

4. The method of claim 1 , wherein prior to performing at least one K n+1 graph, the method comprises: identifying at least one K n graph within the circuit graph, wherein a K n graph comprises a second set of vertices selected from the plurality of vertices connected in series by a second set of edges selected from the plurality of edges and having at least one non-series edge connection between a first vertex and a second vertex selected from the second set of vertices, wherein the second set of vertices comprises n vertices; and merging a third vertex selected from the second set of vertices into a fourth vertex selected from the second set of vertices, wherein the third vertex has a vertex-specific set of edges selected from the second set of edges, and wherein the third vertex is merged into the fourth vertex by removing the third vertex from the circuit graph and adding the vertex-specific set of edges of the third vertex to the fourth vertex to generate the reduced circuit graph.

5. The method of claim 1 , comprising checking the plurality of edges for one or more edges including at least one of a loop or an empty edge.

6. The method of claim 1 , wherein the n-pattern conflict check is selected from the group consisting of: a brute-force n-color check, a heuristic n-pattern conflict check, and a deterministic rules-based conflict check.

7. The method of claim 1 , wherein the Kn+1 graph reduction comprises a square loop reduction process.

8. The method of claim 1 , comprising iteratively identifying one or more additional K n+1 graphs and reducing the one or more additional K n+1 graphs.

9. The method of claim 1 , wherein n is equal to three, and wherein the at least one K n+1 graph is a K 4 graph.

10. The method of claim 1 , wherein n is equal to two, and wherein the at least one K n+1 graph is a K 3 graph.

11. A method, comprising: receiving a circuit layout comprising a plurality of conductive lines; generating a circuit graph representative of the circuit layout, wherein the circuit graph comprises a plurality of vertices and a plurality of edges, wherein each of the plurality of vertices represents one of the plurality of conductive lines, and wherein each of the plurality of edges is representative of a spacing between the conductive lines less than an acceptable minimum distance; coloring the circuit graph with n colors where n is equal to any integer greater than 3, and wherein each of the plurality of vertices is assigned one of the n colors based on an n-patterning checking process including at least one K (n+1) graph reduction; assigning each of the plurality of conductive lines to one of n photomasks based on a color of a corresponding vertex from the plurality of vertices; and forming the n photomasks for use in a n-patterning photolithographic process.

12. The method of claim 11 , wherein the K (n+1) graph reduction comprises removing a set of vertices selected from the plurality of vertices from the circuit graph, wherein each of the set of vertices has less than n edge connections.

13. The method of claim 11 , wherein the n-pattern checking process comprises an n-pattern conflict check selected from the group consisting of: a brute-force n-color coloring, a heuristic n-pattern conflict check, and a deterministic rule-based conflict check.

14. The method of claim 11 , where in the n-pattern checking process comprises at least one square loop reduction.

15. The method of claim 11 , comprising iteratively identifying one or more additional K n+1 graphs and reducing the one or more additional K n+1 graphs.

16. The method of claim 11 , wherein n is an integer greater than or equal to 3.

17. A system configured to generate a plurality of photomasks, the system comprising: a computer configured to: receive a circuit layout comprising a plurality of conductive lines; generate a circuit graph representative of a circuit layout having a plurality of conductive lines, wherein the circuit graph comprises a plurality of vertices and a plurality of edges, wherein each of the plurality of vertices is representative of one of the plurality of conductive lines, and wherein each of the plurality of edges is representative of a spacing between the conductive lines less than an acceptable minimum distance; reduce the circuit graph by one or more K n+1 reductions to generate a reduced circuit graph; and check the reduced circuit graph for one or more triple patterning conflicts, wherein the checking assigns one of three colors to each of the set of vertices in the reduced circuit graph; and a photomask generator configured to generate a first photomask, a second photomask, and a third photomask each comprising a set of the plurality of conductive lines of the circuit layout, wherein each set of the plurality of conductive lines corresponds to one of three colors assigned to the set of vertices, wherein the first color corresponds to the first photomask, the second color corresponds to the second photomask, and the third color corresponds to the third photomask.

18. The system of claim 17 , wherein the computer is configured to remove one or more vertices from the plurality of vertices, wherein the one or more vertices each have less than three edges associated therewith in the plurality of edges.

19. The system of claim 17 , wherein the one or more K n+1 reductions comprises merging a first vertex into a second vertex selected from a first set of the plurality of vertices defining a K n loop, wherein the first vertex has a set of edges selected from the plurality of edges, and wherein the first vertex is merged into the second vertex by removing the first vertex from the circuit graph and adding the set of edges to the second vertex to generate a reduced circuit graph.

20. The system of claim 19 , wherein the first vertex and the second vertex have a largest path separation of pairs of vertices from the first set of the plurality of vertices.