Legal claims defining the scope of protection, as filed with the USPTO.
1. A decoder comprising: a main memory; a flag memory configured to store flag data; and decoding logic configured to perform an iteration comprising: performing an ith operation using first data to obtain second data, i being a natural number, performing a flag encoding operation on the second data, in response to the flag encoding operation being successful, storing in the flag memory a result obtained by the flag encoding operation performed on the second data as first flag data and not storing the second data in the main memory, wherein the first flag data indicates a location of each bit of the first data that has a value of 1, and in response to the flag encoding operation being unsuccessful, storing a predetermined second flag data that is different from the first flag data of the second data in the flag memory and storing the second data in the main memory.
2. The decoder of claim 1 , wherein a size of the first flag data is smaller than a size of the first data and a size of the second data, and a size of the predetermined second flag data is smaller than the size of the first data and the size of the second data.
3. The decoder of claim 1 , wherein a storage capacity of the flag memory is smaller than a storage capacity of the main memory.
4. The decoder of claim 1 , wherein the decoding logic is further configured to: reference the flag data stored in the flag memory; when the referenced flag data is the first flag data, generate the second data by flag decoding the first flag data; when the referenced flag data is the predetermined second flag data, generate the second data by accessing and reading from the main memory; and perform an (i+1)th operation using the generated second data.
5. The decoder of claim 4 , wherein the decoding logic is further configured to reference the flag data during buffer flushing.
6. The decoder of claim 1 , wherein the decoding logic is further configured to transform data having random values into the first data using a syndrome-aided code.
7. The decoder of claim 1 , wherein the flag encoding operation is performed by using a run-length code.
8. The decoder of claim 1 , wherein the main memory is physically separated from the flag memory.
9. The decoder of claim 1 , wherein the first flag data comprises a plurality of bits.
10. A decoder comprising a main memory, a flag memory configured to store flag data, and decoding logic configured to perform an iteration comprising referencing the flag data stored in the flag memory, and generating first data having a size larger than a size of the flag data based on the referenced flag data, and wherein the decoding logic is further configured to: determine whether the referenced flag data is first flag data or predetermined second flag data different from the first flag data, generate the first data by performing a flag decoding operation on the first flag data in response to determining that the referenced flag data is the first flag data, and generate the first data by accessing and reading the main memory in response to determining that the referenced flag data is the predetermined second flag data different from the first flag data.
11. The decoder of claim 10 , wherein the decoding logic is further configured to repeat the referencing the flag memory and the generating the first data for i number of times, wherein i is a natural number.
12. The decoder of claim 10 , wherein the decoding logic is further configured to initialize and generate the first data when the referenced flag data is null.
13. The decoder of claim 10 , wherein the decoding logic is further configured to reference the flag data during buffer flushing.
14. The decoder of claim 10 , wherein the main memory is physically separated from the flag memory.
15. The decoder of claim 10 , wherein the decoding logic is further configured to generate the first data without accessing the main memory in response to determining that the referenced flag data is the first flag data.
16. The decoder of claim 10 , wherein the first flag data indicates a location of each bit of a plurality of bits of the first data that has a value of 1.
17. The decoder of claim 16 , wherein a single bit of the plurality of bits of the first data has the value of 1 and the first flag data comprises a binary representation of the location of the single bit within the plurality of bits.
18. The decoder of claim 17 , wherein the binary representation of the location of the single bit indicates a number of bits from a rightmost bit of the plurality of bits of the first data.
19. The decoder of claim 16 , wherein the first flag data comprises a run-length code indicating a number of consecutive bits in the first data that has the value of 1.
20. The decoder of claim 16 , wherein the first flag data comprises a run-length code indicating a first number of consecutive bits in the first data that have the value of 1 and a second number of consecutive bits in the first data that have a value of 0.
21. A decoder comprising: a main memory; a buffer; a flag memory configured to store flag data; and decoding logic configured to: reference the flag data stored in the flag memory, and determine whether the referenced flag data is first flag data indicating a location of each bit of a plurality of bits of first data that has a value of 1 or predetermined second flag data different from the first flag data, generate the first data by performing a flag decoding operation on the first flag data in response to determining that the referenced flag data is the first flag data, generate the first data by accessing and reading the main memory in response to determining that the referenced flag data is the predetermined second flag data different from the first flag data, perform an operation using the generated first data to obtain second data, store the second data in the buffer, perform a flag encoding operation on the second data, in response to the flag encoding operation being successful, store in the flag memory a result obtained by the flag encoding operation performed on the second data as third flag data, wherein the second data comprises a plurality of bits and the third flag data indicates a location of each of the plurality of bits of the second data that has a value of 1, and in response to the flag encoding operation being unsuccessful, store the predetermined second flag data in the flag memory and store the second data in the main memory.
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June 8, 2021
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