Integrated Circuit and Method of Manufacturing the Same

1. An integrated circuit comprising: a first active region and a second active region in a substrate, the first active region and the second active region being separated from each other in a first direction, and being located on a first level; a third active region in the substrate, the third active region being located on the first level and being separated from the second active region in a second direction different from the first direction; a first contact extending in the second direction, overlapping the first active region, and being located on a second level different from the first level; and a second contact extending in the first direction and the second direction, overlapping the first contact and the third active region, being electrically coupled to the first contact, and being located on a third level different from the first level and the second level.

2. The integrated circuit of claim 1 , further comprising: a third contact extending in the second direction, overlapping the third active region, being located on the second level, and being electrically coupled to the second contact.

3. The integrated circuit of claim 2 , wherein the first active region corresponds to a drain of a first transistor of a first type; the second active region corresponds to a drain of a second transistor of the first type or a source of the first transistor of the first type; and the third active region corresponds to a drain or a source of a third transistor of a second type different from the first type.

4. The integrated circuit of claim 1 , wherein the second contact comprises: a first portion extending in the first direction, overlapping the first contact, the first active region and the second active region; and a second portion extending in the second direction, being electrically coupled to the first portion, and overlapping the second active region and the third active region.

5. The integrated circuit of claim 4 , further comprising: a first insulating region over the second active region, the second active region is not electrically coupled to the second contact.

6. The integrated circuit of claim 4 , further comprising: a fourth active region in the substrate, the fourth active region being separated from the first active region in the first direction, and being located on the first level; a fifth active region in the substrate, the fifth active region being located on the first level and being separated from the fourth active region in the second direction; a third contact extending in the second direction, overlapping the fifth active region, and being located on the second level; and a first insulating region over the fourth active region.

7. The integrated circuit of claim 6 , wherein the second contact further comprises: a third portion extending in the second direction, being separated from the second portion in the second direction, being electrically coupled to the first portion and the second portion, overlapping the fourth active region and the third contact, the third active region being electrically coupled to the second contact, and the fourth active region not being electrically coupled to the second contact.

8. The integrated circuit of claim 1 , wherein the integrated circuit is part of an AND OR INVERT logic circuit.

9. An integrated circuit comprising: a first set of active regions in a substrate, the first set of active regions extending in a first direction, being located on a first level; a second set of active regions in the substrate, the second set of active regions extending in the first direction, being located on the first level, and being separated from the first set of active regions in a second direction different from the first direction; a first set of contacts extending in the second direction, overlapping at least the first set of active regions or the second set of active regions, and being located on a second level different from the first level, each of the contacts of the first set of contacts being separated from an adjacent contact of the first set of contacts in the first direction, the first set of contacts being electrically coupled to at least the first set of active regions or the second set of active regions; and a second set of contacts extending in the first direction and the second direction, overlapping the first set of contacts, and being located on a third level different from the first level and the second level, the second set of contacts being electrically coupled to a first contact of the first set of contacts.

10. The integrated circuit of claim 9 , wherein the second set of contacts comprises: a second contact comprising: a first portion extending in the first direction, overlapping the first contact of the first set of contacts, a first active region and a second active region of the first set of active regions, the first active region of the first set of active regions being electrically coupled to the first contact of the first set of contacts; and a second portion extending in the second direction, being electrically coupled to the first portion, and overlapping the second active region of the first set of active regions and a first active region of the second set of active regions.

11. The integrated circuit of claim 10 , wherein the first set of contacts comprises: a third contact extending in the second direction, overlapping and electrically coupled to the first active region of the second set of active regions, and being electrically coupled to the second contact.

12. The integrated circuit of claim 11 , further comprising: an insulating region over the second active region of the first set of active regions, the second contact being electrically isolated from the second active region of the first set of active regions.

13. The integrated circuit of claim 10 , wherein the second contact has a L-shape, a U-shape, a T-shape or a W-shape.

14. The integrated circuit of claim 9 , further comprising: a set of gates extending in the second direction, overlapping the first set of active regions and the second set of active regions, and being located on the second level, each of the gates of the set of gates being separated from an adjacent gate of the set of gates in the first direction by a first pitch.

15. The integrated circuit of claim 9 , further comprising: a first set of conductive structures extending in at least the first direction, being located on a fourth level different from the first level, the second level and the third level, and at least overlapping the first set of contacts or the second set of contacts.

16. The integrated circuit of claim 15 , further comprising: a first set of vias coupling the first set of conductive structures to the first set of contacts, the first set of vias being between the first set of conductive structures and the first set of contacts, and a via of the first set of vias being located where a conductive structure of the first set of conductive structures overlaps the first contact of the first set of contacts; and a second set of vias coupling the first set of conductive structures to the second set of contacts, the second set of vias being between the first set of conductive structures and the second set of contacts, and a via of the second set of vias being located where another conductive structure of the first set of conductive structures overlaps a second contact of the second set of contacts.

17. The integrated circuit of claim 9 , further comprising: a set of power rails extending in at least the first direction, being located on a fourth level different from the first level, the second level and the third level, and overlapping the first set of contacts; and a first set of vias coupling the set of power rails to the first set of contacts, the first set of vias being between the set of power rails and the first set of contacts, and a via of the first set of vias being located where a power rail of the set of power rails overlaps a second contact of the first set of contacts.

18. A method of forming an integrated circuit (IC), the method comprising: generating, by a processor, a cell layout design of the integrated circuit, wherein the generating of the cell layout design comprises: generating a set of active region layout patterns extending in a first direction, being located on a first layout level, and being separated from one another in a second direction different from the first direction, the set of active regions layout patterns corresponding to fabricating a set of active regions in a substrate; generating a set of gate layout patterns extending in the second direction, overlapping the set of active region layout patterns, and being located on a second layout level different from the first layout level, each of the gate layout patterns of the set of gate layout patterns being separated from an adjacent gate layout pattern of the set of gate layout patterns in the first direction, the set of gate layout patterns corresponding to fabricating a set of gates; generating a first set of contact layout patterns extending in the second direction, overlapping the set of active region layout patterns, and being located on the second layout level, each of the contact layout patterns of the first set of contact layout patterns being separated from an adjacent contact of the first set of contact layout patterns in the first direction, the first set of contact layout patterns corresponding to fabricating a first set of contacts, the first set of contacts being electrically coupled to the set of active regions; and generating a second set of contact layout patterns extending in the first direction and the second direction, overlapping the first set of contact layout patterns, and being located on a third layout level different from the first layout level and the second layout level, the second set of contact layout patterns corresponding to fabricating a second set of contacts, the second set of contacts being electrically coupled to the first set of contacts; and manufacturing the integrated circuit based on the cell layout design.

19. The method of claim 18 , wherein generating of the cell layout design further comprises: generating a first set of conductive structure layout patterns extending in the first direction or the second direction, overlapping the set of gate layout patterns, and being located on a fourth layout level different from the first layout level, the second layout level and the third layout level, and the first set of conductive structure layout patterns corresponding to fabricating a first set of conductive structures.

20. The method of claim 19 , wherein generating of the cell layout design further comprises: generating a first set of via layout patterns corresponding to fabricating a first set of vias, the first set of via layout patterns being between the first set of conductive structure layout patterns and the first set of contact layout patterns, and a via layout pattern of the first set of via layout patterns being located where a conductive structure layout pattern of the first set of conductive structure layout patterns overlaps a contact layout pattern of the first set of contact layout patterns, the first set of vias coupling the first set of conductive structures to the first set of contacts; and generating a second set of via layout patterns corresponding to fabricating a second set of vias, the second set of via layout patterns being between the first set of conductive structure layout patterns and the second set of contact layout patterns, and a via layout pattern of the second set of via layout patterns being located where another conductive structure layout pattern of the first set of conductive structure layout patterns overlaps a contact layout pattern of the second set of contact layout patterns, the second set of vias coupling the first set of conductive structures to the second set of contacts.