Memory Controller, Memory System and Application Processor Comprising the Memory Controller

1. A memory controller configured to control a memory device including a plurality of memory pages, the memory controller comprising: an error correction code (ECC) region manager configured to manage the plurality of memory pages by dividing the plurality of memory pages into ECC enable regions and ECC disable regions; an ECC cache configured to store ECC data; and an ECC engine configured to perform an ECC operation on data included in the ECC enable regions, wherein, when data and data address are received from outside the memory controller and the ECC enable regions include the data address, the ECC engine performs the ECC operation on the received data, when the ECC disable regions include the data address, the ECC engine does not perform the ECC operation on the received data, and a hit/miss detection content addressable memory of the ECC cache detects whether there is a hit between an address of data to be read and an address stored in the ECC cache.

2. The memory controller of claim 1 , wherein the ECC region manager is configured to store information on the ECC enable regions as region data.

3. The memory controller of claim 2 , further comprising: an ECC decider configured to receive the region data and determine whether to deliver data input to the memory controller to the ECC engine based on the region data.

4. The memory controller of claim 1 , wherein the ECC region manager is configured to receive, from outside the memory controller, a region decision control signal for identifying the ECC enable regions.

5. The memory controller of claim 1 , further comprising an ECC cache configured to store ECC data.

6. The memory controller of claim 5 , wherein the ECC cache is configured to store the ECC data for each bank of the memory device.

7. An application processor comprising: a processor; and a memory controller configured to control an external memory device comprising a plurality of memory pages, the memory controller configured to receive data addresses from the processor, the memory controller configured to receive data from the external memory device or the processor, and the memory controller configured to determine, based on the data address, whether to perform ECC operation on the received data, wherein the memory controller includes an ECC cache configured to store ECC data, and a hit/miss detection content addressable memory of the ECC cache detects whether there is a hit between an address of data to be read and an address stored in the ECC cache.

8. The application processor of claim 7 , wherein the memory controller comprises: an ECC engine configured to perform the ECC operation; and an ECC decider configured to determine whether the ECC engine is to perform the ECC operation on the received data based on the data address, wherein the ECC decider is configured to transmit the received data to the ECC engine in response to the received data indicating to perform the ECC operation.

9. The application processor of claim 8 , wherein the memory controller further comprises: an ECC region manager configured to manage the plurality of memory pages by dividing the plurality of memory pages into ECC enable regions and ECC disable regions.

10. The application processor of claim 9 , wherein the processor is configured to transmit to the memory controller a region decision control signal for identifying the ECC enable regions and the ECC disable regions.

11. The application processor of claim 9 , wherein the ECC region manager is configured to store information on the ECC enable regions as region data, and the ECC decider is configured to determine whether the ECC engines performs the ECC operation on the received data based on the data address and the region data.

12. The application processor of claim 9 , wherein the processor is configured to determine whether the data requires the ECC operation, the processor assigns the data address to the ECC enable regions in response to the data requiring the ECC operation, and the processor assigns the data address to the ECC disable regions in response to the data not requiring the ECC operation.

13. The memory controller of claim 1 , wherein the memory device includes a volatile memory device.

14. The application processor of claim 8 , wherein the external memory device includes a volatile memory device.