Flash Memory Controller Which Assigns Address and Sends Assigned Address to Host in Connection with Data Write Requests for Use in Issuing Later Read Requests for the Data

1. A memory controller for flash memory, the memory controller comprising: a host interface to receive a request that causes the memory controller to write data and to receive a later data read request from a host for the data; logic to assign, in connection with the request that causes the memory controller to write the data, an address in the flash memory, to write the data into the flash memory at a location corresponding to the assigned address, and to transmit the assigned address to the host; and logic to control execution of the later data read request in the flash memory, wherein the later data read request is accompanied by a read address effective to specify the location in the flash memory to serve as an operand for the later data read request, wherein the read address is dependent on the assigned address transmitted to the host by the memory controller; and a memory interface to issue commands to the flash memory in order to execute the write of the data and the later data read request; wherein each said logic comprises at least one of hardware circuitry or instructions stored on non-transitory machine-readable media that are to control the function of hardware circuitry.

2. The memory controller of claim 1 , wherein: the flash memory comprises a structural hierarchy, including storage structures at a first tier and storage structures at a second tier, each of the structures of the first tier being associated with a respective subset of the structures at the second tier; the request that causes the memory controller to write the data is a data write request; the data write request comprises a host designation of one of the storage structures at one of the first tier and the second tier; the assigned address represents a memory controller-selection of one of the storage structures at the other of the first tier and the second tier; and the read address is dependent on both of the host designation and the memory controller-selection.

3. The memory controller of claim 1 , wherein: the request which causes the memory controller to write the data is a request to copy existing data from a source physical storage location in the flash memory to a destination physical storage location in the flash memory; and the assigned address corresponds to the destination physical storage location.

4. The memory controller of claim 3 , wherein: the memory controller comprises logic to track and update storage location release information for plural independently erasable storage locations in the flash memory; the logic to track and update is to update the storage release information for the source physical storage location in response to the request to copy existing data; the memory controller comprises logic to determine based on the storage location release information, as updated, that one of the plural independently erasable storage locations is a candidate for erasure; the memory controller comprises logic to transmit to the host information indicating that, at a time convenient for the host, one or more of the plural independently erasable storage locations should be erased; and the memory controller comprises logic to erase the one or more of the plural independently erasable storage locations in response to receipt, via the host interface, of an erasure request from the host that specifies a non-exhaustive portion of the flash memory to be erased.

5. The memory controller of claim 3 , wherein: the memory controller further comprises logic to track and update storage location release information for plural independently erasable storage locations in the flash memory; the memory controller further comprises logic to compare the storage location release information with a threshold, to identify at least one of the plural independently erasable storage locations in the flash memory that is a candidate for garbage collection and to transmit information to the host that, at timing convenient for the host, each identified garbage collection candidate should be garbage collected; and the request which causes the memory controller to copy the existing data is a request for garbage collection, and is responsive to the information transmitted to the host by the memory controller.

6. The memory controller of claim 1 , wherein: the memory controller further comprises logic to track and update metadata for plural storage locations in the flash memory, the metadata representing a hot-versus cold status of an item of data stored at a corresponding one of the storage locations; the memory controller further comprises logic to compare the metadata with a threshold, to identify at least one of the storage locations for which the corresponding item is a predetermined one of relatively hot or relatively cold, and to transmit information to the host that, at timing convenient for the host, an item at the identified at least one of the storage locations should be relocated; and the request which causes the memory controller to write the data is a request to relocate at least one identified item, and which causes the memory controller, responsive to the request to relocate the at least one identified item, to read the data from a source location in the flash memory and write the data at the location corresponding to the assigned address without sending the data to the host.

7. The memory controller of claim 1 , wherein: the memory controller further comprises logic to copy existing data from a source physical storage location in the flash memory to a destination physical storage location in the flash memory; and the logic to copy is to assign a new address for the data being copied, corresponding to the destination physical storage location, and to transmit the assigned new address to the host; and a later second read request for the data being copied includes a second-host-supplied address which is dependent on the assigned new address.

8. A memory controller for flash memory, wherein the flash memory comprises independently writable storage locations, the memory controller comprising: a host interface to receive a request that causes the memory controller to write data and to receive a later data read request from a host for the data; logic to assign, in connection with the request that causes the memory controller to write the data, a specific one of the independently writable storage locations in which to write the data, to control programming of the data into the specific one of the independently writable storage locations, and to thereby assign to the accompanying data an address corresponding to the specific one of the independently writeable storage locations, and to transmit the assigned address to the host; and logic to control execution of the later data read request in the flash memory, wherein the later data read request from the host is accompanied by a read address effective to specify the location in the flash memory to serve as an operand for the later data read request, so as to retrieve the accompanying data, wherein the read address is dependent on the assigned address transmitted to the host by the memory controller; and a memory interface to issue commands to the flash memory in order to execute the writing of the data and the later data read request; wherein each said logic comprises at least one of hardware circuitry or instructions stored on non-transitory machine-readable media that are to control the function of hardware circuitry.

9. The memory controller of claim 8 , wherein: the flash memory comprises a structural hierarchy, including storage structures at a first tier and storage structures at a second tier, each of the structures of the first tier being associated with a respective subset of the structures at the second tier; the request that causes the memory controller to write the data is a data write request; the data write request comprises a host designation of one of the storage structures at one of the first tier and the second tier; the assigned address represents a memory controller-selection of one of the storage structures at the other of the first tier and the second tier; and the read address is dependent on both of the host designation and the memory controller-selection.

10. The memory controller of claim 8 , wherein: the request which causes the memory controller to write the data is a request to copy existing data from a source physical storage location in the flash memory to a destination physical storage location in the flash memory; and the assigned address corresponds to the destination physical storage location.

11. The memory controller of claim 10 , wherein: the memory controller comprises logic to track and update storage location release information for plural independently erasable storage locations in the flash memory; the logic to track and update is to update the storage release information for the source physical storage location in response to the request to copy existing data; the memory controller comprises logic to determine based on the storage location release information, as updated, that one of the plural independently erasable storage locations is a candidate for erasure; the memory controller comprises logic to transmit to the host information indicating that, at a time convenient for the host, one or more of the plural independently erasable storage locations should be erased; and the memory controller comprises logic to erase the one or more of the plural independently erasable storage locations in response to receipt, via the host interface, of an erasure request from the host that specifies a non-exhaustive portion of the flash memory to be erased.

12. The memory controller of claim 10 , wherein: the memory controller further comprises logic to track and update storage location release information for plural independently erasable storage locations in the flash memory; the memory controller further comprises logic to compare the storage location release information with a threshold, to identify at least one of the plural independently erasable storage locations in the flash memory that is a candidate for garbage collection and to transmit information to the host that, at timing convenient for the host, each identified garbage collection candidate should be garbage collected; and the request which causes the memory controller to copy the existing data is a request for garbage collection, and is responsive to the information transmitted to the host by the memory controller.

13. The memory controller of claim 8 , wherein: the memory controller further comprises logic to track and update metadata for plural storage locations in the flash memory, the metadata representing a hot-versus cold status of an item of data stored at a corresponding one of the storage locations; the memory controller further comprises logic to compare the metadata with a threshold, to identify at least one of the storage locations for which the corresponding item is a predetermined one of relatively hot or relatively cold, and to transmit information to the host that, at timing convenient for the host, an item at the identified at least one of the storage locations should be relocated; and the request which causes the memory controller to write the data is a request to relocate at least one identified item, and which causes the memory controller, responsive to the request to relocate the at least one identified item, to read the data from a source location in the flash memory and write the data at the location corresponding to the assigned address without sending the data to the host.

14. The memory controller of claim 8 , wherein: the memory controller further comprises logic to copy existing data from a source physical storage location in the flash memory to a destination physical storage location in the flash memory; and the logic to copy is to assign a new address for the data being copied, corresponding to the destination physical storage location, and to transmit the assigned new address to the host; and a later second read request for the data being copied includes a second-host-supplied address which is dependent on the assigned new address.

15. A memory controller for a flash memory system, wherein the flash memory system comprises flash memory having independently writable storage locations and independently erasable storage locations, each of the independently erasable storage locations corresponding to a respective subset of the independently writable storage locations, the memory controller comprising: a host interface to receive a data write request and to receive a later data read request from a host; logic to assign, in connection with the data write request, a specific one of the independently writable storage locations in which to write accompanying data, to control execution of the data write request by commanding the programming of the accompanying data into the specific one of the independently writable storage locations, and to thereby assign to the accompanying data an address corresponding to the specific one of the independently writeable storage locations, and to transmit the assigned address to the host; and logic to control execution of the later data read request in the flash memory, wherein the later data read request is accompanied by a read address effective to specify the location in the flash memory to serve as an operand for the later data read request, so as to retrieve the accompanying data, wherein the read address is dependent on the assigned address transmitted to the host by the memory controller; logic to maintain metadata for each of the independently erasable storage locations which identifies the extent to which the respective subset of the independently writable storage locations has been marked as released; and logic to control execution of an address-delimited host-issued erasure request, received via the host interface, and to control erasure of one or more of the independently erasable storage locations corresponding to the address delimitation; a memory interface to issue commands to the flash memory in order to execute the data write request, the later data read request, the host-issued erasure request; wherein each said logic comprises at least one of hardware circuitry or instructions stored on non-transitory machine-readable media that are to control the function of hardware circuitry.

16. The memory controller of claim 15 , wherein: the flash memory comprises a structural hierarchy, including storage structures at a first tier and storage structures at a second tier, each of the structures of the first tier being associated with a respective subset of the structures at the second tier; the data write request comprises a host designation of one of the storage structures at one of the first tier and the second tier; the assigned address represents a memory controller-selection of one of the storage structures at the other of the first tier and the second tier; and the read address is dependent on both of the host designation and the memory controller-selection.

17. The memory controller of claim 15 , wherein: the memory controller further comprises logic to copy existing data from a source physical storage location in the flash memory to a destination physical storage location in the flash memory; and the logic to copy is to assign a new address for the data being copied, corresponding to the destination physical storage location, and to transmit the assigned new address to the host; and a later second read request for the data being copied includes a second-host-supplied address which is dependent on the assigned new address.

18. The memory controller of claim 17 , wherein: the memory controller further comprises logic to compare the metadata with a threshold, to identify at least one of the independently erasable storage locations in the flash memory that is a candidate for garbage collection and to transmit information to the host that, at timing convenient for the host, each identified garbage collection candidate should be garbage collected; and the request which causes the memory controller to copy the existing data is a request for garbage collection, and is responsive to the information transmitted to the host by the memory controller.

19. The memory controller of claim 15 , wherein: the metadata also encompasses information representing a hot-versus cold status of an item of data stored at a corresponding one of the storage locations; the memory controller further comprises logic to compare the information representing the hot-versus-cold status with a threshold, to identify at least one of the storage locations for which the corresponding item is a predetermined one of relatively hot or relatively cold, and to transmit information to the host that, at timing convenient for the host, an item at the identified at least one of the storage locations should be relocated; and the memory controller further comprises logic to receive a request from the host to relocate at least one identified item, and which causes the memory controller, responsive to the request to relocate the at least one identified item, to read the data from a source location in the flash memory and write the data at the location corresponding to the assigned address without sending the data to the host.

20. The memory controller of claim 15 , wherein the flash memory system comprises channels which each are to couple the memory controller with a respective subset of flash memory dies, and wherein said memory controller is embodied as a flash memory controller integrated circuit.

21. The memory controller of claim 1 , wherein the memory controller is further to receive an erase request from the host that specifies a host-address-selection, and wherein the memory controller further comprises logic to responsively control erasure of an integer number of erase blocks representing a subset of storage locations in the flash memory that corresponds to the host-address selection.

22. The memory controller of claim 21 , wherein the host-address selection is dependent on at least one assigned address transmitted to the host for data which has previously been written in at the location corresponding to the assigned address.

23. The memory controller of claim 8 , wherein the memory controller is further to receive an erase request from the host that specifies a host-address-selection, and wherein the memory controller further comprises logic to responsively control erasure of an integer number of erase blocks representing a subset of storage locations in the flash memory that corresponds to the host-address selection.

24. The memory controller of claim 23 , wherein the host-address selection is dependent on at least one assigned address transmitted to the host for data which has previously been written in at the location corresponding to the assigned address.

25. The memory controller of claim 15 , wherein the memory controller is further to receive an erase request from the host that specifies a host-address-selection, and wherein the memory controller further comprises logic to responsively control erasure of an integer number of erase blocks representing a subset of storage locations in the flash memory that corresponds to the host-address selection.

26. The memory controller of claim 25 , wherein the host-address selection is dependent on at least one assigned address transmitted to the host for data which has previously been written in at the location corresponding to the assigned address.

27. The memory controller of claim 1 , wherein in connection with the request to write the data, the host is to specify an address of a structure at a superior hierarchical level of the nonvolatile memory as a write destination, wherein the assigned address represents an assignment by the memory controller of a structure at an inferior hierarchical level of the nonvolatile memory as a write destination, and wherein the read address is effective to specify each of the structure at the superior hierarchical level of the nonvolatile memory and the structure at the inferior hierarchical level of the nonvolatile memory.

28. The memory controller of claim 8 , wherein in connection with the request to write the data, the host is to specify an address of a structure at a superior hierarchical level of the nonvolatile memory as a write destination, wherein the assigned address represents an assignment by the memory controller of a structure at an inferior hierarchical level of the nonvolatile memory as a write destination, and wherein the read address is effective to specify each of the structure at the superior hierarchical level of the nonvolatile memory and the structure at the inferior hierarchical level of the nonvolatile memory.

29. The memory controller of claim 15 , wherein in connection with the request to write the data, the host is to specify an address of a structure at a superior hierarchical level of the nonvolatile memory as a write destination, wherein the assigned address represents an assignment by the memory controller of a structure at an inferior hierarchical level of the nonvolatile memory as a write destination, and wherein the read address is effective to specify each of the structure at the superior hierarchical level of the nonvolatile memory and the structure at the inferior hierarchical level of the nonvolatile memory.