Method for Simulating Signal Integrity of Hybrid Model

1. A method for simulating signal integrity of a hybrid model, comprising: establishing a transient simulation link, wherein the transient simulation link comprises a front-end chip model, a pre-link model arranged at an output end of the front-end chip model and a terminating impedance model arranged at a tail end of the pre-link model, and the front-end chip model is a Spice model; inputting an ideal step signal to a port reserved in the front-end chip model, and extracting step response data in a steady state outputted from the tail end of the pre-link model; inputting the step response data to an input end of a channel simulation link, wherein the channel simulation link comprises a relay chip model, a back-end chip model and a post-link model for connecting the relay chip model and the back-end chip model, and each of the relay chip model and the back-end chip model is an IBIS AMI model; and inputting a random code signal to the input end of the channel simulation link, and reading a signal outputted from an output end of the back-end chip model and forming an eye pattern.

2. The method according to claim 1 , wherein the pre-link model and/or the post-link model is a model using S-parameters.

3. The method according to claim 2 , wherein the pre-link model and/or the post-link model is a wiring model having a length of 5 inches.

4. The method according to claim 1 , further comprising: reading a signal outputted from an output end of the post-link model and forming an eye pattern.

5. The method according to claim 2 , further comprising: reading a signal outputted from an output end of the post-link model and forming an eye pattern.

6. The method according to claim 3 , further comprising: reading a signal outputted from an output end of the post-link model and forming an eye pattern.