Method for Improved Cut Metal Patterning

1. A system for preparing an integrated circuit device design comprising: a first memory configured for storing a plurality of preliminary integrated circuit design files; a processor configured and programmed for retrieving a preliminary integrated circuit design file from the first memory; locating a first vertical abutment between an m th device cell design and an n th device cell design from the preliminary integrated circuit design file; identifying a first internal metal cut in the m th device cell design and a second internal metal cut in the n th device cell design; determining a horizontal spacing between the first internal metal cut and the second internal metal cut; evaluating whether the horizontal spacing satisfies a spacing threshold; and if the spacing threshold is not satisfied, shifting the n th cell design horizontally relative to the m th cell design by a distance equal to N contacted polysilicon pitch (CPP) to define a modified device layout, wherein N is an integer; repeating the determining, evaluating, and shifting operations until the spacing threshold is satisfied; and identifying a next vertical abutment between an (m+1) th device cell design and an (n+1) th device cell design from the preliminary integrated circuit design file and repeating the identifying, determining, shifting operations until the spacing threshold has been satisfied for all located vertical abutments.

2. The system for preparing an integrated circuit device design according to claim 1 , further comprising: a second memory configured for receiving an upload of the modified device layout that satisfies the spacing threshold.

3. The system for preparing an integrated circuit device design according to claim 2 , wherein: the first memory and the second memory are provided in a single memory device.

4. The system for preparing an integrated circuit device design according to claim 1 , further comprising: an output device arranged and configured to set communicate a fail condition when the modified device layout fails to satisfy the spacing threshold.

5. The system for preparing an integrated circuit device design according to claim 1 , wherein: the processor is further configured and programmed for determining a maximum number of modified device layouts to be evaluated before determining that the modified device layout fails to satisfy the spacing threshold.

6. The system according to claim 1 , further comprising: a second processor arranged and configured for retrieving a final modified device layout and generating a tape out.

7. The system according to claim 6 , further comprising: a mask house arranged and configured for receiving the tape out and producing a plurality of masks corresponding to the modified device layout.

8. The system according to claim 1 , wherein: N is at least 4.

9. A system for preparing an integrated circuit device design comprising: a first memory configured for storing a plurality of device cell designs; a processor configured and programmed for retrieving a first device cell design and a second device cell design from the memory; arranging the first and second device cells in a vertically abutting configuration in an initial device layout; identifying a first internal metal cut in the first device cell design and a first safe region on the first device cell design; identifying a second internal metal cut in the second device cell design; determining a horizontal spacing between the first internal metal cut and the second internal metal cut in the initial device layout; determining whether the horizontal spacing satisfies a spacing threshold; and if the spacing threshold is not satisfied, shifting the second cell design horizontally relative to the first cell design to place the second internal metal cut under the first safe zone and thereby define a modified device layout; and evaluating the modified device layout to ensure that the spacing threshold is satisfied.

10. The system according to claim 9 , further comprising: identifying a second safe region on the first device cell design; identifying a second internal metal cut in the second device cell design; determining a horizontal spacing between the first internal metal cut and the second internal metal cut in the initial device layout; determining whether the horizontal spacing satisfies a spacing threshold; and if the spacing threshold is not satisfied, shifting the second cell design horizontally relative to the first cell design to place the second internal metal cut under the first safe zone or the second safe zone and thereby define the modified device layout.

11. A system for manufacturing an integrated circuit device comprising: a first memory configured for storing a plurality of device cell designs; a processor configured for retrieving a first device cell design and a second device cell design from the memory; arranging the first and second device cells in a vertically abutting configuration in an initial device layout; identifying a first internal metal cut in the first device cell design; identifying a second internal metal cut in the second device cell design; determining a horizontal spacing between the first internal metal cut and the second internal metal cut in the initial device layout; determining whether the horizontal spacing satisfies a spacing threshold; and if the spacing threshold is not satisfied, shifting the second cell design horizontally relative to the first cell design by a distance equal to N contacted polysilicon pitch (CPP) to define a modified device layout, wherein N is an integer; and repeating the determining, evaluating, and shifting operations until the modified device layout satisfies the spacing threshold; a second memory configured for storing the modified device layout; a mask house configured for retrieving the modified device layout from the second memory and fabricating a plurality of masks corresponding to the modified device layout.

12. The system according to claim 11 , wherein: N is at least 4.

13. The system for manufacturing an integrated circuit device according to claim 11 , further comprising: a device foundry having a front end of line (FEOL) manufacturing facility arranged and configured using the plurality of masks, in conjunction with doping, deposition, lithography, and etching operations, to manufacture the integrated device.

14. The system for manufacturing an integrated circuit device according to claim 13 , wherein: the device foundry further comprises a back end of line (BEOL) manufacturing facility arranged and configured for the testing, interconnection, and packaging of the integrated device.

15. The system for manufacturing an integrated circuit device according to claim 14 , wherein: the BEOL manufacturing facility utilizes an electronic process control (EPC) system.

16. The system for manufacturing an integrated circuit device according to claim 13 , wherein: the FEOL manufacturing facility utilizes an electronic process control (EPC) system.

17. The system for manufacturing an integrated circuit device according to claim 11 , wherein: the mask house is arranged and configured for providing optical proximity correction (OPC) to at least one of the plurality of masks for improving a patterned image accuracy.

18. The system for manufacturing an integrated circuit device according to claim 11 , wherein: the mask house is arranged and configured for providing at least one resolution enhancement techniques (RET) selected from the group consisting of off-axis illumination, sub-resolution assist features, phase-shifting masks to at least one of the plurality of masks for improving a patterned image accuracy.

19. The system for manufacturing an integrated circuit device according to claim 11 , wherein: the mask house is arranged and configured for applying an inverse lithography technique to at least one of the plurality of masks for improving a patterned image accuracy.

20. The system for manufacturing an integrated circuit device according to claim 11 , wherein: processor comprises a portion of an electronic design automation (EDA) tool.