User Device Including a Nonvolatile Memory Device and a Data Write Method Thereof

1. A storage device comprising: a nonvolatile memory device including a plurality memory blocks, each of the plurality of memory blocks including a plurality of cell strings; and a controller configured to receive mode information from a host to write the mode information into a single register, wherein the controller is further configured to receive a write command from the host, and control the nonvolatile memory device to perform a write operation in response to which the mode information is written into the single register, wherein the write operation is performed in a first mode when the mode information is set, by the host, into the single register, wherein the write operation is performed in a second mode, the second mode being a default mode for the storage device, wherein the mode information is provided frons the host, through a separate command other than the write command, wherein the write operation performed in the first mode includes a program operation using lower program voltages, wherein the write operation performed in the second mode includes a program operation using normal program voltages, wherein a lifetime of the nonvolatile memory device in the first mode is increased more than a lifetime of the nonvolatile memory device in the second mode, wherein the nonvolatile memory device or the controller is packaged by a Ball Grid Array (BGA) package, wherein the mode information is based on an ON/OFF state of a display, an ON/OFF state of a User interface and an input state of a user input of the user interface.

2. The storage device of claim 1 , wherein the write operation in the second mode is faster than the write operation in the first mode.

3. The storage device of claim 1 , wherein the single register is written based on information corresponding to the second mode before receiving the mode information from the host.

4. The storage device of claim 1 , wherein the nonvolatile memory device is further configured to receive a control signal for the mode information from the controller, and adjust voltages used in the write operation in response to the control signal.

5. The storage device of claim 1 , wherein the nonvolatile memory device is further configured to: when the write operation is performed in the first mode, perform the write operation on the at least one of the plurality of memory blocks, using first programming voltages and first verify voltages; and when the write operation is performed in the second mode, perform the write operation on the at least one of the plurality of memory blocks using second programming voltages and second verify voltages.

6. The storage device of claim 5 , wherein the first verify voltages are different from the second verify voltages, respectively.

7. The storage device of claim 5 , wherein the first program voltages are lower than the second programming voltages.

8. The storage device of claim 5 , wherein the controller is further configured to control the nonvolatile memory device to erase at least one of the plurality of memory blocks before performing the write operation, wherein the nonvolatile memory device is further configured to: when the write operation is performed in the first mode, erase the at least one of the plurality of memory blocks using first erase voltages and first erase verify voltages; and when the write operation is performed in the second mode, erase the at least one of the plurality of memory blocks using second erase voltages and second erase verify voltages.

9. The storage device of claim 8 , wherein the first erase voltages are lower than the second erase voltages, respectively, and the first erase verify voltages are higher than the second erase voltages, respectively.

10. The storage device of claim 8 , wherein the first erase voltages are equal to the second erase voltages, respectively, and the first erase verify voltages are equal to the second erase verify voltages respectively, and wherein the first programming voltages are lower than the second programming voltages, respectively and the first verify voltages are lower than the second verify voltages, respectively.

11. The storage device of claim 1 , wherein the controller is further configured to receive a new access command from the host during the write operation in the first mode, and delay a process for the new access command until the write operation is completed.

12. The storage device of claim 1 , wherein the controller is further configured to manage an effective wearing for each of the plurality of memory blocks.

13. The storage device of claim 12 , wherein when the write operation is performed in the first mode, the controller accumulates the effective wearing based on a first value, and wherein the write operation is performed in the second mode, the controller accumulates the effective wearing based on a second value greater than the first value.

14. The storage device of claim 13 , wherein the controller is further configured to perform a wear leveling or a garbage collection based on the effective wearing.

15. The storage device of claim 1 , wherein the mode information is set by the host based on an operation mode of a user device in which the storage device is included, and wherein the operation mode of the user device includes at least one of a screen saver mode, a lock mode, and a power saving mode.

16. The storage device of claim 1 , wherein the mode information is set by the host when the maximum operation speed of the storage device is not required.

17. The storage device of claim 1 , wherein the mode information is set by the host based on integrity or retention characteristics of write data corresponding to the write command.

18. A storage device comprising: a nonvolatile memory device; and a controller configured to receive mode information, which is set by a host, from the host, write the mode information into a single register, and perform a first access operation on the nonvolatile memory device in response to which the mode information is written to the single register, wherein the first access operation includes a program operation using lower program voltages, wherein the controller is further configured to per a second access operation on the nonvolatile memory device, the second access operation being based on a default mode for the storage device, wherein the second access operation includes a program operation using normal program voltages, wherein a lifetime of the nonvolatile memory device in a case where the first access operation is performed is increased more than a lifetime of the nonvolatile memory device in a case where the second access operation is performed, wherein the mode information is received from the host through a separate command other than a write command, wherein the nonvolatile memory device or the controller is packaged by a Ball Grid Array (BGA) package, wherein the mode information is based on an ON/OFF state of a display, an ON/OFF state of a user interface and an input state of a user input of the user interface.

19. The storage device of claim 13 , wherein the nonvolatile memory device comprises: a cell array including a plurality memory blocks, each of the plurality of memory blocks including a plurality of cell strings; a decoder connected to the cell array through wordlines, string selection lines, and ground selection lines; and a page buffer connected to the cell array through bitlines.

20. The storage device of claim 18 , wherein the controller is further configured to transmit a control signal to the nonvolatile memory device in response to which the mode information is written to the single register, and the nonvolatile memory device comprises an element configured to adjust direct current (DC) voltage in response to the received control signal.

21. The storage device of claim 18 , wherein the lower program voltages are lower than the normal program voltages, and wherein first verify voltages used in the program operation included in the first access operation are different from second verify voltages used in the program operation included in the second access operation.

22. The storage device of claim 18 , wherein the first access operation includes a first erase operation using a first erase voltage and first erase verify voltages, wherein the second access operation includes a second erase operation using a second erase voltage and second erase verify voltages, and wherein the first erase verify voltages are different from the second erase verify voltages.

23. The storage device of claim 18 , wherein each of memory cells, to which the first access operation is subjected, has one of a first erase state and first program states, and each of memory cells, to which the second access operation is performed has one of a second erase state and second program states, and wherein differences between a threshold distribution corresponding to the first erase state with each of threshold distributions corresponding to the first program states is less than differences between a threshold distribution corresponding to the second erase state with each of threshold distributions corresponding to the second program states, respectively.

24. The storage device of claim 18 , wherein the second access, operation is faster than the first access operation.

25. The storage device of claim 18 , wherein the controller is further configured to manage an effective wearing for each of the plurality of memory blocks.

26. The storage device of claim 25 , wherein when the first access operation is performed, the controller accumulates the effective wearing based on a first value, and when the second access operation is performed, the controller accumulates the effective wearing based on a second value greater than the first value.

27. The storage device of claim 26 , wherein the controller is further configured to perform a wear leveling or a garbage collection based on the effective wearing.

28. The storage device of claim 18 , wherein the mode information is set by the host based on an operation mode of a user device in which the storage device is included, and wherein the operation mode of the user device includes at least one of a screen saver mode, a lock mode, and a power saving mode.

29. The storage device of claim 18 , wherein the mode information is set by the host when the maxim operation speed of the storage device is not required.

30. A storage controller comprising, a host interface configured to receive a write command from a host; a memory interface configured to communicate with a nonvolatile memory device; and a processing unit configured to control the memory interface to perform a write operation on the nonvolatile memory device in response to the write command, wherein the write operation is performed in a first mode, when mode information is set, by the host, into a single register, wherein the write operation is performed in a second mode, the second mode being a default mode, wherein the mode information is received from the host through a separate command other than the write command, wherein the write operation in the first mode is performed using lower program voltages, wherein the write operation in the second mode is performed using normal program voltages, wherein a lifetime of the nonvolatile memory device in the second mode is increased more than a lifetime of the nonvolatile memory device in the first mode, wherein the storage controller is packaged by a Ball Grid Array (BGA) package, wherein the mode information is based on an ON/OFF state of a display, an ON/OFF state of a user interface and an input state of a user input of the user interface.