Memory System, Semiconductor Integrated Circuit, and Method Therefor

1. A memory system comprising: a first nonvolatile memory; a first bridge circuit connected to the first nonvolatile memory; a second nonvolatile memory; a second bridge circuit connected to the second nonvolatile memory and connected to the first bridge circuit; and a controller connected to the first bridge circuit and configured to output, to the first bridge circuit, first data to be stored in the first nonvolatile memory and second data to be stored in the second nonvolatile memory, the first and second data being mapped to one or more multiplexing symbols, each of the multiplexing symbols including a pair of symbols corresponding to a pair of a most significant bit and a least significant bit, the first data being mapped to either one of the most significant bit and the least significant bit, the second data being mapped to the other of the most significant bit and the least significant bit, wherein the first bridge circuit is configured to upon receipt of the multiplexing symbols, extract the first data from the multiplexing symbols, store the first data in the first nonvolatile memory, generate third data using either: one of a most significant bit and a least significant bit corresponding to each of the symbols to which the second data is mapped, or an inverted bit of the one of the most significant bit and the least significant bit, and insert the generated third data into the multiplexing symbols to which the first data was mapped, and output to the second bridge circuit the multiplexing symbols into which the third data has been inserted.

2. The memory system according to claim 1 , wherein the controller comprises a multiplexer configured to upon receipt of data from a host, encode most significant bits and least significant bits based on the received data such that a DC balance of the encoded most significant and least significant bits is maintained, and map the encoded most significant and least significant bits to the multiplexing symbols using linear mapping.

3. The memory system according to claim 2 , wherein each of the multiplexing symbols includes PAM4 symbols.

4. The memory system according to claim 1 , wherein the controller is configured to output header data including a synchronization code mapped to one or more multiplexing symbols.

5. The memory system according to claim 4 , wherein The synchronization code is mapped to 2 symbols of the multiplexing symbols.

6. The memory system according to claim 4 , wherein the synchronization code is mapped to 3 symbols of the multiplexing symbols.

7. The memory system according to claim 4 , wherein each bit of data included in a first symbol and a second symbol of the multiplexing symbols of the header is encoded independently of each other.

8. The memory system according to claim 1 , wherein the multiplexing symbols include a first multiplexing symbol to which the first data is mapped and a second multiplexing symbol to which the second data is mapped, the controller is configured to output first header data corresponding to the first data and second header data corresponding to the second data, the first and second header data mapped to a third and a fourth multiplexing symbol, respectively, and the second header data includes a synchronization code including two PAM4 symbols that cause a zero crossing transition when modulated into a signal in PAM communication.

9. The memory system according to claim 8 , wherein the third data generated by the first bridge circuit is a synchronization code including two PAM4 symbols that cause a zero crossing transition when modulated into a signal in PAM communication.

10. The memory system according to claim 8 , wherein the third data is determined according to values of preceding or subsequent symbols to the symbol that were extracted by the first bridge circuit.

11. The memory system according to claim 1 , further comprising: a third nonvolatile memory; a third bridge circuit connected to the third nonvolatile memory and connected to the second bridge circuit; a fourth nonvolatile memory; and a fourth bridge circuit connected to the fourth nonvolatile memory and connected to the third bridge circuit, wherein the controller is configured to output the first data, the second data, fourth data to be stored in the third nonvolatile memory, and fifth data to be stored in the fourth nonvolatile memory, the first, second, fourth, and fifth data mapped to a first, a second, a third, and a fourth multiplexing symbol, respectively, the fourth, second, third, and first multiplexing symbols being arranged in this order, and after the controller outputs the multiplexing symbols, the first, second, third, and fourth bridge circuits extract the first, second, fourth, and fifth data, respectively.

12. The memory system according to claim 11 , wherein the controller is configured to generate first, second, third, and fourth header data corresponding to the first, second, fourth, and fifth data, respectively, the first, second, third, and fourth header data being mapped to a fifth, a sixth, a seventh, and an eighth multiplexing symbol, respectively, the eighth, sixth, seventh, and fifth multiplexing symbols being arranged in this order, and the fourth header data includes a DC control bit for controlling a DC balance of the fifth data, and the first, second, and third header data each include three DC control bits for controlling a DC balance of the first, second, and fourth data.

13. The memory system according to claim 1 , wherein the first and second data are multiplexed in at least a time direction, the multiplexing symbols include a first multiplexing symbol including four symbols for storing a first portion of the first data by two adjacent symbols in the time direction and a first portion of the second data by the other two adjacent symbols in the time direction, and a second multiplexing symbol including four symbols for storing a second portion of the first data by two adjacent symbols in the time direction and a second portion of the second data by the other two adjacent symbols in the time direction, and the controller is configured to output first header data corresponding to the first data and second header data corresponding to the second data, the first and second header data being mapped to a plurality of multiplexing symbols including a third multiplexing symbol including four symbols and to which a first portion of the first header data is mapped using two adjacent symbols in the time direction and a first portion of the second header data is mapped using two adjacent symbols in the time direction, and a fourth multiplexing symbol including four symbols and to which a second portion of the first header data is mapped using two adjacent symbols in the time direction and a second portion of the second header data is mapped using two adjacent symbols in the time direction, and the first portion of the first header data includes a synchronization code represented by 01 or 10.

14. The memory system according to claim 13 , wherein the first bridge circuit is configured to upon receipt of the multiplexing symbols from the controller, extract the first and second portions of the first data from the first and second multiplexing symbols, store the first and second portions of the first data in the first nonvolatile memory, insert the first and second portions of the second data or inverted first and second portions of the second data into the first and second multiplexing symbols where the first and second portions of the first data were stored, and output to the second bridge circuit the multiplexing symbols into which the first and second portions of the first data or inverted first and second portions of the second data have been inserted data.

15. The memory system according to claim 14 , wherein the inserted first and second portions of the second data are represented by 01 or 10.

16. The memory system according to claim 13 , wherein the first bridge circuit is configured to upon receipt of the multiplexing symbols from the controller, extract the first and second portions of the first data from the first and second multiplexing symbols, store the first and second portions of the first data in the first nonvolatile memory, generate fourth data based on data adjacent to the extracted first and second portions of the first data, insert the fourth data into the first and second multiplexing symbols where the first and second portions of the first data were stored, and output to the second bridge circuit the multiplexing symbols into which the fourth data has been inserted.

17. The memory system according to claim 13 , wherein the first and second portions of the first header data includes three DC control bits for controlling a DC balance of the first data, and the first and second portions of the second header data includes three DC control bits for controlling the DC balance of the second data, and wherein the controller is configured to output another header data corresponding to another data, the another header data including two DC control bits for controlling the DC balance of the another data.

18. A semiconductor integrated circuit connectable to a first nonvolatile memory and another semiconductor integrated circuit connectable to a second nonvolatile memory different from the first nonvolatile memory, comprising: a first circuit by which one or more multiplexing symbols to which first data to be stored in the first nonvolatile memory and second data to be stored in the second nonvolatile memory are mapped, are received, each of the multiplexing symbols including a pair of symbols corresponding to a pair of a most significant bit and a least significant bit, the first data being mapped to either one of the most significant bit and the least significant bit, the second data being mapped to the other of the most significant bit and the least significant bit; and a second circuit configured to upon receipt of the multiplexing symbols, extract the first data from the multiplexing symbols, store the first data in the first nonvolatile memory, generate third data using either: one of a most significant bit and a least significant bit corresponding to each of the symbols to which the second data is mapped, or an inverted bit of the one of the most significant bit and the least significant bit, and insert the generated third data into the multiplexing symbols to which the first data was mapped, and output to said another semiconductor integrated circuit the multiplexing symbols into which the third data has been inserted.

19. A method for storing data in a memory system including a first nonvolatile memory, a first bridge circuit connected to the first nonvolatile memory, a second nonvolatile memory, and a second bridge circuit connected to the second nonvolatile memory and the first bridge circuit, the method comprising: outputting first data to be stored in the first nonvolatile memory and second data to be stored in the second nonvolatile memory, the first and second data being mapped to one or more multiplexing symbols, each of the multiplexing symbols including a pair of symbols corresponding to a pair of a most significant bit and a least significant bit, the first data being mapped to either one of the most significant bit and the least significant bit, the second data being mapped to the other of the most significant bit and the least significant bit; receiving the multiplexing symbols by the first bridge circuit; extracting the first data from the multiplexing symbol; storing the first data in the first nonvolatile memory; generating third data using either: one of a most significant bit and a least significant bit corresponding to each of the symbols to which the second data is mapped, or an inverted bit of the one of the most significant bit and the least significant bit, and insert the generated third data into the multiplexing symbol at a location to which the first data was mapped; and outputting the multiplexing symbol into which the third data has been inserted, to the second bridge circuit.