System, Apparatus And Method For Dynamically Controlling Error Protection Features Of A Processor

1. A system on chip (SoC) comprising: a graphics processor; a communication circuit; a core including one or more execution units and a first memory array having a first protection circuit to provide soft error protection; and a protection control circuit, in response to an update to an operating voltage to be provided to the core, to cause the first protection circuit to be disabled, wherein when the first protection circuit is disabled, the SoC is to have a reduced dynamic capacitance.

2. The SoC of claim 1 , wherein the protection control circuit is, in response to a determination that the update to the operating voltage exceeds a first threshold, to send a disable signal to cause the first protection circuit to be disabled.

3. The SoC of claim 2 , wherein the protection control circuit is, in response to a determination that the update to the operating voltage exceeds a second threshold, to cause a plurality of protection circuits to be disabled.

4. The SoC of claim 2 , wherein in response to a determination that a second update to the operating voltage is less than the first threshold, the core is to enable the first protection circuit.

5. The SoC of claim 1 , wherein the reduced dynamic capacitance is to enable the core to operate at a higher operating voltage.

6. The SoC of claim 1 , further comprising a power controller to cause the update to the operating voltage in response to a request from another entity.

7. The SoC of claim 6 , wherein the power controller is to cause the operating voltage to be provided to the first protection circuit when enabled, and to prevent the operating voltage from being provided to the first protection circuit when disabled.

8. The SoC of claim 6 , wherein the power controller is to cause the update to the operating voltage to be provided to the core in response to receipt of an acknowledgement that the first protection circuit has been disabled.

9. The SoC of claim 1 , wherein the core further comprises one or more register files, at least one of the one or more registers files having a protection circuit associated therewith.

10. The SoC of claim 9 , wherein the protection circuit associated with a first register file is to be disabled when the operating voltage to be provided to the core exceeds a first threshold.

11. The SoC of claim 1 , wherein the first memory array is to be flushed before the first protection circuit is disabled.

12. The SoC of claim 1 , wherein the first protection circuit is to provide at least one of parity protection and error correction coding protection to the first memory array.

13. A non-transitory machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising: determining whether an updated operating voltage at which a processing circuit of a processor is to operate exceeds a first threshold; in response to determining that the updated operating voltage exceeds the first threshold, identifying at least one protection circuit of the processing circuit to disable; sending a protection disable command to the processing circuit to cause the at least one protection circuit to be disabled; and thereafter causing an update to the operating voltage to the updated operating voltage, after receiving an acknowledgement of the protection disable command.

14. The non-transitory machine-readable medium of claim 13 , wherein the method further comprises: determining whether the updated operating voltage exceeds a second threshold, the second threshold greater than the first threshold; and in response to determining that the updated operating voltage exceeds the second threshold, identifying a plurality of protection circuits to disable.

15. The non-transitory machine-readable medium of claim 13 , wherein the method further comprises in response to determining that a second updated operating voltage at which the processing circuit is to operate is less than the first threshold, sending a protection enable command to cause the processing circuit to re-enable the at least one protection circuit.

16. A system comprising: a processor having a plurality of cores, wherein a first core includes one or more execution units, a first cache memory, a first protection circuit to provide soft error protection, and a control engine to disable the first protection circuit based at least in part on a first operating voltage of the first core, wherein the control engine is to thereafter enable the first protection circuit based at least in part on a second operating voltage of the first core; a voltage regulator to provide one or more operating voltages to the processor; a power controller to control the voltage regulator to provide the one or more operating voltages; and a system memory coupled to the processor.

17. The system of claim 16 , wherein responsive to a read operation to the first cache memory, the first core is to read data and perform a parity check based on parity information associated with the data when the first protection circuit is enabled, and read the data and not perform the parity check when the first protection circuit is disabled.

18. The system of claim 16 , wherein the power controller comprises a power management integrated circuit coupled to the processor.

19. The system of claim 16 , wherein the processor further comprises a shared cache memory, the shared cache memory separate from the first cache memory and having another protection circuit comprising parity circuitry and error correction coding circuitry.

20. The system of claim 19 , wherein the processor further comprises at least one redundant structure to operate in lockstep based at least in part on the first operating voltage of the first core.