Electronic Device

1. An electronic device including a semiconductor memory, the semiconductor memory comprising: a memory cell array of a plurality of memory cells each including a variable resistance element exhibiting different resistance values representing different digital information and outputting, to a corresponding bit line, a cell voltage corresponding to a resistance value of the variable resistance element; a driving control circuit coupled to the memory cell array and operable to control a reference data to be written in a selected memory cell among the memory cells, during a sensing operation; a resistance monitoring circuit coupled to the memory cell array and operable to output a monitoring voltage by monitoring, during a write operation for writing the reference data, a change in the resistance value based on the cell voltage at the bit line; and an amplifying circuit coupled to the resistance monitoring circuit and operable to amplify the monitoring voltage and output an amplified monitoring voltage as output data.

2. The electronic device according to claim 1 , wherein the variable resistance element is configured to store different data depending on whether the variable resistance element has a high resistance state or a low resistance state.

3. The electronic device according to claim 1 , wherein the resistance monitoring circuit includes: a differential circuit configured to differentiate the cell voltage and output the monitoring voltage based on the change of the cell voltage.

4. The electronic device according to claim 1 , wherein the semiconductor memory further includes: a level adjusting circuit configured to adjust a level of the monitoring voltage and transfer the adjusted monitoring voltage to the amplifying circuit.

5. The electronic device according to claim 4 , wherein the resistance monitoring circuit is configured to output the monitoring voltage having a positive value (+), a value of 0, or a negative value (−).

6. The electronic device according to claim 1 , wherein the resistance monitoring circuit includes: a capacitor coupled between an input terminal receiving the cell voltage and an output terminal outputting the monitoring voltage; and a resistor coupled between the output terminal and a ground voltage terminal.

7. The electronic device according to claim 1 , wherein the resistance monitoring circuit includes: a first transistor coupled between a supply voltage terminal and a first node, and having a gate receiving a voltage of the first node; a second transistor coupled between the first node and a ground voltage terminal, and having a gate receiving the cell voltage; a capacitor coupled between the first node and an output terminal outputting the monitoring voltage; and a resistor coupled between the output terminal and the ground voltage terminal.

8. The electronic device according to claim 1 , wherein the resistance monitoring circuit includes: a capacitor coupled between an input terminal receiving the cell voltage and a second node; an operational amplifier configured to receive a voltage of the second node as a negative input terminal and a ground voltage as a positive input terminal, and output the monitoring voltage to an output terminal; and a resistor coupled between the second node and the output terminal.

9. The electronic device according to claim 1 , wherein the resistance monitoring circuit includes: a first monitor circuit configured to operate in response to a signal activated when the reference data has a high resistance state and to output the monitoring voltage by monitoring the change in the resistance value according to the cell voltage; and a second monitor circuit configured to operate in response to a signal activate suitable for outputting the monitoring voltage by monitoring the change in the resistance value according to the cell voltage, in case where the reference data is ‘low’ data.

10. The electronic device according to claim 9 , wherein the first monitor circuit includes: a capacitor coupled between an input terminal receiving the cell voltage and an output terminal outputting the monitoring voltage; and a resistor coupled between the output terminal and a ground voltage terminal.

11. The electronic device according to claim 9 , wherein the first monitor circuit includes: a first transistor coupled between a supply voltage terminal and a first node, and having a gate receiving a voltage of the first node; a second transistor coupled between the first node and a ground voltage terminal, and having a gate receiving the cell voltage; a capacitor coupled between the first node and an output terminal outputting the monitoring voltage; and a resistance element coupled between the output terminal and the ground voltage terminal.

12. The electronic device according to claim 9 , wherein the second monitor circuit includes: a capacitor coupled between an input terminal receiving the cell voltage and a second node; an operational amplifier configured to receive a voltage of the second node as a negative input terminal and a ground voltage as a positive input terminal, and to output the monitoring voltage to an output terminal; and a resistance element coupled between the second node and the output terminal.

13. The electronic device according to claim 1 , wherein the driving control circuit is configured to allow an original data stored in the selected memory cell to be written, after the sensing operation, back to the selected memory cell based on the output data, wherein a read operation for reading the original data from the selected memory cell is omitted before and during the sensing operation.

14. The electronic device according to claim 13 , wherein the driving control circuit is configured to allow the original data to be written back to the selected memory cell when the output data indicates that there exists the change in the resistance value during the sensing operation.

15. The electronic device according to claim 1 , wherein the driving control circuit includes: at least one current source configured to provide a read current or a write current to the bit line coupled to the selected memory cell.

16. The electronic device according to claim 1 , wherein the amplifying circuit includes inverters that are cross coupled.

17. The electronic device of claim 1 , further comprising a microprocessor which includes: a control unit configured to receive a signal including a command from an outside of the microprocessor, and performs extracting, decoding of the command, or controlling input or output of a signal of the microprocessor; an operation unit configured to perform an operation based on a result that the control unit decodes the command; and a memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed, wherein the semiconductor memory is part of the memory unit in the microprocessor.

18. The electronic device of claim 1 , further comprising a processor which includes: a core unit configured to perform, based on a command inputted from an outside of the processor, an operation corresponding to the command, by using data; a cache memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed; and a bus interface connected between the core unit and the cache memory unit, and configured to transmit data between the core unit and the cache memory unit, wherein the semiconductor memory is part of the cache memory unit in the processor.

19. The electronic device of claim 1 , further comprising a processing system which includes: a processor configured to decode a command received by the processor and control an operation for information based on a result of decoding the command; an auxiliary memory device configured to store a program for decoding the command and the information; a main memory device configured to call and store the program and the information from the auxiliary memory device such that the processor can perform the operation using the program and the information when executing the program; and an interface device configured to perform communication between at least one of the processor, the auxiliary memory device and the main memory device and the outside, wherein the semiconductor memory is part of the auxiliary memory device or the main memory device in the processing system.

20. The electronic device of claim 1 , further comprising a data storage system which includes: a storage device configured to store data and conserve stored data regardless of power supply; a controller configured to control input and output of data to and from the storage device according to a command inputted form an outside; a temporary storage device configured to temporarily store data exchanged between the storage device and the outside; and an interface configured to perform communication between at least one of the storage device, the controller and the temporary storage device and the outside, wherein the semiconductor memory is part of the storage device or the temporary storage device in the data storage system.

21. The electronic device of claim 1 , further comprising a memory system which includes: a memory configured to store data and conserve stored data regardless of power supply; a memory controller configured to control input and output of data to and from the memory according to a command inputted form an outside; a buffer memory configured to buffer data exchanged between the memory and the outside; and an interface configured to perform communication between at least one of the memory, the memory controller and the buffer memory and the outside, wherein the semiconductor memory is part of the memory or the buffer memory in the memory system.

22. A method of operating an electronic device having a semiconductor memory, comprising: writing a reference data in a selected memory cell among memory cells included in the semiconductor memory, each memory cell including a variable resistance element that exhibits either high or low resistance value; outputting a monitoring voltage by monitoring, during the writing of the reference data, a change in a resistance value of the selected memory cell based on a cell voltage at a bit line coupled to the selected memory cell; and amplifying the monitoring voltage and outputting the amplified monitoring voltage as output data.

23. The method of claim 22 , wherein the monitoring of the change in the resistance value of the selected memory cell includes: differentiating the cell voltage to output the monitoring voltage.

24. The method of claim 22 , further comprising: writing the original data to the selected memory cell based on the output data, wherein a reading operation for reading the original data from the selected memory cell is omitted before the writing of the original data to the selected memory cell.

25. The method of claim 24 , wherein the writing of the original data is performed when the output data indicates that there exists the change in the resistance value.

26. The method of claim 22 , further comprising: adjusting a level of the monitoring voltage.

27. The method of claim 26 , wherein the adjusted level of the monitoring voltage has a positive value (+), a value of 0, or a negative value (−).