Apparatus and Method and Computer Program Product for Configuring Impedance of Memory Interfaces

1. A method for configuring impedance of memory interfaces, performed by a processing unit when loading and executing program codes of a software or firmware module, wherein the processing unit is coupled to a memory interface, a static random access memory (SRAM) and a calibration interface, the memory interface is coupled to a memory device and comprises a first transmitter and a first receiver, and the memory device comprises a second transmitter and a second receiver, the method comprising: setting a first impedance value associated with an on-die termination (ODT) for the first receiver to a first default value for a first training process, wherein the first receiver of the memory interface of a controller receives signals from the second transmitter of the memory device; setting a second impedance value associated with a driver variable resistance for the second transmitter to a second default value for the first training process; performing tests for a plurality of first test combinations for the first training process, in which each first test combination comprises a third impedance value associated with a driver variable resistance for the first transmitter and a fourth impedance value associated with an ODT for the second receiver, wherein the first transmitter of the memory interface of the controller sends signals to the second receiver of the memory device; and storing a test result for each first test combination in a predefined location of the SRAM, thereby enabling a calibration host to obtain the test result for each first test combination from the SRAM through the calibration interface, wherein the first training process comprises a plurality of iterations, and each iteration corresponding to one first test combination comprises: varying the driver variable resistance for the first transmitter according to the corresponding third impedance value: varying the our for the second receiver according to the corresponding fourth impedance value; and performing the tests when the ODT for the first receiver is fixed to the first default value, and the driver variable resistance for the second transmitter is fixed to the second default value.

2. The method of claim 1 , comprising: receiving a command with impedance settings from the calibration host, wherein the impedance settings are determined by the calibration host according to the test results for the first test combinations; and programming the impedance settings into non-volatile storage space of the controller and the memory device as factory settings, wherein the controller comprises the processing unit.

3. The method of claim 1 , wherein the test results for the first test combinations are stored in a data, table, comprising, a first axis and a second axis, the first axis is associated with, signal strengths related to, the ODT of the memory device sorted from the strongest to the weakest or from the weakest to the strongest, and the second axis is associated with signal strengths related to a driver of the memory interface sorted from the strongest to the weakest or from the weakest to the strongest.

4. The method of claim 3 , wherein the data table comprises a plurality of bytes and each byte records a test result when a driver variable resistance of the memory interface is set to a fifth impedance value and an ODT of the memory device set to a sixth impedance value.

5. The method of claim 4 , wherein ach byte being a first value represents that a test-write-then-read on a test area of storage space of the memory device has failed.

6. The method of claim 4 , wherein each byte being a second value represents that a read timeout happens when the processing instructs the memory interface to perform a random read-write test, each byte being a third value represents that a write timeout happens when the processing unit instructs the memory interface to perform a random read-write test, and each byte being a fourth value represents that read-back data is different from previously programmed data whet the processing unit instructs the memory interface to perform a random read-write test.

7. The method of claim 1 , comprising: setting a fifth impedance value associated with the ODT for the second receiver to a third default value for a second training process, where in the second receiver receives signals from the first transmitter of the memory interface of the controller; setting a sixth impedance value associated driver variable stance for the first transmitter to a fourth default value for the second training process; performing tests for a plurality of second test combinations for the second training process, in which each second test combination comprises a seventh impedance value associated with the driver variable resistance for the second transmitter and an eighth impedance value associated with the ODT for the first receiver, wherein the second transmitter of the memory d sends signals to the first receiver of the memory interface of the controller; and storing a test result for each second test combination in a predefined location the SRAM, thereby enabling the calibration host to obtain the test result for each second test combination from the SRAM through the calibration interface.

8. The method of claim 7 , comprising: receiving a command with impedance settings from the calibration host, wherein the impedance settings are determined by the calibration host according to the test results for the first and second test combinations; and programming the impedance settings into non-volatile storage space of the controller and the memory device as factor settings, wherein the controller comprises the processing unit.

9. A non-transitory computer program product for configuring impedance of memory interfaces when executed by a processing unit, wherein the processing unit is coupled to a memory interface, a static random access memory (SRAM) and a calibration interface, the memory interface is coupled to a memory device and comprises a first transmitter and a first receiver, and the memory device comprises a second transmitter and a second receiver, the non-transitory computer program product comprising program code to: set a first impedance value associated with an on-die termination (ODT) for the first receiver to a first default value for a first training process, wherein the first receiver of the memory interface of a controller receives signals from the second transmitter of the memory device; set a second, impedance value associated with a dr variable resistance for the second transmitter to a second default value for the first training process; perform tests for a plurality of first test combinations for the first training process, in which each first test combination comprises a third impedance value associated with a driver variable resistance for the first transmitter and a fourth impedance value associated with an ODT for second receiver, wherein the first transmitter of the memory interface of the controller sends signals to the second receiver of the memory device; and store a test result for each first test combination in a predefined location of the SRAM, thereby enabling a calibration host to obtain the test result for each first test combination from the SRAM through the calibration interface, wherein the first training process comprises a plurality of iterations, and each, iteration corresponding to one first test combination comprises: varying the driver variable resistance for the first transmitter according to the corresponding third impedance value; varying the ODT for the second receiver according to the corresponding fourth impedance value; and performing tests when the ODT for the first receiver is fixed to the first default value, and, the driver variable resistance for the second transmitter is fixed to the second default value.

10. The non-transitory computer program product of claim 9 , comprising program code to: receive a command with impedance settings from the calibration host, wherein the impedance settings are determined by the calibration host according to the test result for the first test combinations; and program the impedance settings into non-volatile storage space of the controller and the memory device as factory settings, wherein the controller comprises the processing unit.

11. The non-transitory computer program product of claim 9 , wherein the test results for the first test combinations are stored in a data, table comprising a first axis and a second axis, the first axis is associated signal strengths related to the ODT of the memory device sorted from the strongest to the weakest or from the weakest to the strongest, and the second axis is associated with signal strengths related to a driver of the memory interface sorted from the strongest to the weakest or from the weakest to the strongest.

12. The non-transitory computer program product of claim 11 , wherein the data table comprises a plurality of bytes and each byte records a test result when a driver variable resistance of the memory interface is set to a fifth impedance value and an ODT of the memory device is set to a sixth impedance value.

13. The non-transitory computer program product of claim 12 , wherein each byte being a first value represents that a test-write-then-read on a test area of storage space of the memory device has failed.

14. The non-transitory computer program product of claim 12 , wherein each byte being a second value represents that a read timeout happens when the processing unit instructs the memory interface to perform a random read-write test, each byte being a third value represents that a write timeout happens when the processing unit instructs the memory interface to perform a random read-write test, and each byte being a fourth value represents that read-back data is different from previously programmed data when the processing unit instructs the memory interface to perform a random read-write test.

15. An apparatus for configuring impedance of memory interfaces, comprising: a controller, comprising: a memory interface, coupled to a memory device, comprising a first transmitter and a first receiver; and a calibration interface, coupled to a host; a static random access memory (SRAM); and a processing unit, coupled to the memory interface, the calibration interface and the SRAM, arranged to operably set a first impedance value associated with an on-die termination (ODT) for the first receiver to a first default value for a first training process, wherein the first receiver receives signals from a second transmitter of the memory device; set a second impedance value associated with a driver variable resistance for the second transmitter to a second default value for the first training process; perform tests for a plurality of first test combinations for the first training process, in which each first test combination comprises a third impedance value associated with a driver variable resistance for the first transmitter and a fourth impedance value associated with an ODT for the second receiver, wherein the first transmitter sends signals to a second receiver of the memory device; and store a test result for each first test combination in a predefined location of the SRAM, thereby enabling a calibration host to obtain the test result for each first test combination from the SRAM through the calibration interface, wherein the first training process comprises a plurality of iterations, and each iteration corresponding to one first test combination comprises: varying the driver variable resistance for the first transmitter according to the corresponding third impedance value; varying the ODT for the second receiver according to the corresponding fourth impedance value; and performing the tests when the ODT for the first receiver is fixed to the first default value, and the driver variable resistance for the second transmitter is fixed to the second default value.

16. The apparatus of claim 15 , comprising: the host, arranged to operably determine impedance settings according to the test results for the first test combinations and issue a command with the impedance settings to the controller through the calibration interface, wherein the processing unit arranged to operably program the impedance settings into non-volatile storage space of the controller and the memory device as factory settings.

17. The apparatus of claim 15 , wherein the test results for the first test combinations are stored in a data table comprising a first axis and a second axis, the first axis is associated with signal strengths related to the ODT of the memory device sorted from the strongest to the weakest or from the weakest to the strongest, and the second axis is associated with signal strengths related to a driver of the memory interface sorted from the strongest to the weakest or from the weakest to the strongest.

18. The apparatus f claim 17 , wherein the data table comprises a plurality of bytes and each byte records a test when a driver variable resistance of the memory interface is set to a fifth impedance value and an ODT of the memory device is set to a sixth impedance value.

19. The apparatus of claim 18 , wherein each byte being a first value represents that a test-write-then-read on a test area of storage space of the memory device has failed.

20. The apparatus of claim 18 , wherein each byte being a second value represents that a read timeout happens when the processing unit is arranged operably to instruct the memory interface to perform a random read-write test, each byte being a third value represents that a write timeout happens when the processing unit is arranged, operably to instruct the memory interface to perform a random read-write test, and each byte being a fourth value represents that read-back data is different from previously programmed data when the processing unit is arranged operably to instruct the memory interface to perform a random read-write test.