Legal claims defining the scope of protection, as filed with the USPTO.
1. A systolic processor comprising: a systolic array of processing elements arranged in rows and columns, each row of the systolic array including a plurality of row-oriented buses; wherein the systolic array of processing elements is divided into a first sub-array of processing elements and a second sub-array of processing elements, each sub-array of processing elements including one or more consecutive columns of the systolic array, each sub-array of processing elements further including, for each row, an active row-oriented bus and one or more inactive row-oriented busses, each processing element configured to perform a mathematical operation on an input of the active row-oriented bus corresponding to the respective sub-array; a first shifter element interposed between the first and second sub-arrays, wherein the first shifter element comprises circuitry configured, for each row of the array, to shift a data element transmitted on an inactive bus of the first sub-array to an active bus of the second sub-array; wherein each processing element is further configured to: perform the mathematical operation on a weight and an input data element, and provide the weight and the input data element to a subsequent column of the respective sub-array.
2. The systolic processor of claim 1 , wherein the systolic processor further comprises a pipelining block of pipelining registers, wherein the pipelining block is configured to store a plurality of inputs for one or more systolic intervals and provide the plurality of inputs to the active bus and the one or more inactive busses of the first sub-array.
3. The systolic processor of claim 1 , wherein each sub-array of processing elements includes, for each row, a plurality of active row-oriented busses.
4. The systolic processor of claim 1 , wherein the first shifter element comprise a plurality of pipelining registers, each pipelining register configured to store an output of the first sub-array for one or more systolic intervals.
5. The systolic processor of claim 1 further comprising a second shifter element, the second shifter element located before the first sub-array, the second shifter element comprising circuitry configured, for each row of the array, to provide an input for each of the active bus and the one or more inactive busses of the first sub-array.
6. A systolic processor comprising: a systolic array of processing elements arranged in rows and columns; wherein the systolic array of processing elements is divided into a plurality of sub-arrays of processing elements, each sub-array of the processing elements including a plurality of consecutive columns of the systolic array, each sub-array of the processing elements further including, for each row, an active bus and one or more inactive busses, each processing element of a sub-array configured to perform a mathematical operation on an input of the active bus corresponding to the respective sub-array; and a plurality of shifter elements dispersed within the systolic array, each shifter element comprising circuitry configured, for each row of the array, to obtain an output and provide the output to an active bus of a sub-array.
7. The systolic processor of claim 6 , wherein the active bus and the one or more inactive busses comprise a plurality of row-oriented busses.
8. The systolic processor of claim 6 , wherein each sub-array of the processing elements includes, for each row, a plurality of active busses.
9. The systolic processor of claim 6 , wherein each processing element is further configured to: perform the mathematical operation on a weight and an input data element; and provide the weight and the input data element to a subsequent column of the respective sub-array.
10. The systolic processor of claim 6 , wherein the systolic processor further comprises a pipelining block of pipelining registers in a plurality of pipelining busses, wherein the pipelining block is configured to store a plurality of inputs for one or more systolic intervals and provide the plurality of inputs to the active bus and the one or more inactive busses of a first sub-array.
11. The systolic processor of claim 10 , wherein a number of pipelining registers within a respective row of the pipelining block is based on a number of sub-arrays of the plurality of sub-arrays.
12. The systolic processor of claim 10 , wherein a number of pipelining busses of the pipelining block is based on a number of busses of the active bus and the one or more inactive busses.
13. The systolic processor of claim 6 , wherein each shifter element comprises a plurality of pipelining registers, the plurality of pipelining registers configured to store a plurality of inputs for one or more systolic intervals.
14. The systolic processor of claim 6 , wherein the plurality of shifter elements includes a first shifter element configured, for each row of the systolic array, to receive a first input and provide the first input to an active bus of a first sub-array.
15. The systolic processor of claim 6 , wherein the plurality of shifter elements includes a first shifter element configured, for each row of the systolic array, to obtain an output from an inactive bus of a first sub-array and provide the output to an active bus of a second sub-array.
16. The systolic processor of claim 6 , wherein a number of consecutive columns of the plurality of consecutive columns is based on a distance that a row-oriented bus can be driven in a clock cycle.
17. The systolic processor of claim 6 , wherein the systolic array includes m columns, wherein the plurality of sub-arrays includes n sub-arrays, wherein the plurality of consecutive columns includes m/n consecutive columns.
18. A systolic processor comprising: a systolic array of processing elements arranged in rows and columns, each row of the systolic array including a plurality of row-oriented busses, each row-oriented bus corresponding to a number of consecutive processing elements; wherein each row-oriented bus is configured as an active row-oriented bus for a subset of consecutive columns of the systolic array, each processing element of the subset of consecutive columns of the systolic array configured to perform a mathematical operation on an input of the active row-oriented bus; and a plurality of shifter elements, each shifter element configured to select a row-oriented bus for a given subset of consecutive columns, wherein selecting the row-oriented bus comprises selecting the row-oriented bus for the active row-oriented bus of the given subset of consecutive columns, each shifter element interposed within the systolic array.
19. The systolic processor of claim 18 , wherein the systolic array is divided into a plurality of sub-arrays based on a number of the plurality of row-oriented busses.
20. The systolic processor of claim 18 , wherein the systolic processor further comprises a pipelining block of pipelining registers, wherein the pipelining registers are configured to store a plurality of inputs for one or more systolic intervals and provide the plurality of inputs to a first column of the systolic array.
21. The systolic processor of claim 20 , wherein a number of pipelining registers within the pipelining block is based on a number of row-oriented busses.
22. The systolic processor of claim 18 , wherein each processing element is configured to perform a mathematical operation on an input of the respective active row-oriented bus.
23. The systolic processor of claim 22 , wherein each processing element is further configured to: perform the mathematical operation on a weight and an input data element; and provide the weight and the input data element to a subsequent column of the given subset of consecutive columns.
24. The systolic processor of claim 18 , wherein each shifter element comprises a plurality of pipelining registers, the plurality of pipelining registers configured to store a plurality of inputs for one or more systolic intervals.
25. The systolic processor of claim 18 , wherein the plurality of shifter elements includes a first shifter element configured, for each row of the systolic array, to select a first row-oriented bus for the active bus of a first subset of consecutive columns.
26. The systolic processor of claim 25 , wherein the plurality of shifter elements includes a second shifter element configured, for each row of the systolic array, to select a second row-oriented bus for the active bus of a second subset of consecutive columns, wherein the first subset of consecutive columns is separated from the second subset of consecutive columns by at least the second shifter element.
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September 7, 2021
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