Serialization Floors and Deadline Driven Control for Performance Optimization of Asymmetric Multiprocessor Systems

1. A method of controlling performance of one or more processors or coprocessors of an asymmetric multiprocessor system, the method comprising: executing a thread group on a processor and a coprocessor of the asymmetric multiprocessor system, wherein the thread group has a first control effort parameter corresponding to the processor and a second control effort parameter corresponding to the coprocessor; and at least one of: performing a hysteretic adjustment of the first control effort parameter to slow a transition of the processor to a low power state while a workload associated with the thread group is executing on the coprocessor; or performing a hysteretic adjustment of the second control effort parameter to slow a transition of the coprocessor to a low power state while the workload associated with the thread group is executing on the processor.

2. The method of claim 1 wherein the hysteretic adjustment of at least one of the first control effort parameter and the second control effort parameter includes delaying a time between the workload being submitted to the coprocessor and decreasing the first control effort parameter.

3. The method of claim 1 wherein the hysteretic adjustment includes decreasing a rate at which the first control effort parameter decreases.

4. The method of claim 1 wherein the processor is selected from the group consisting of a central processing unit, a graphics processing unit, a general purpose graphics processing unit, a neural engine, an image signal processor, and a scaling and rotating engine.

5. The method of claim 1 wherein the coprocessor is selected from the group consisting of a central processing unit, a graphics processing unit, a general purpose graphics processing unit, a neural engine, an image signal processor, and a scaling and rotating engine.

6. The method of claim 1 wherein the first and second control effort parameters respectively affect at least one of an allocated subset of cores or execution units and a dynamic voltage and frequency state of the processor or the coprocessor.

7. An asymmetric multiprocessor system comprising: a processor complex comprising one or more processors; one or more coprocessors; a closed loop performance controller configured to control performance of the one or more processors and the one or more coprocessors; and an operating system executing on the processor complex, the operating system comprising an input/output service interactive with the closed loop performance controller and one or more drivers corresponding to the one or more coprocessors; wherein the closed loop performance controller is configured to cooperate with the operating system, the processor complex, and the one or more coprocessors to: execute a thread group on a processor and a coprocessor of the asymmetric multiprocessor system, wherein the thread group has a first control effort parameter corresponding to the processor and a second control effort parameter corresponding to the coprocessor; and at least one of: perform a hysteretic adjustment of the first control effort parameter to slow a transition of the processor to a low power state while a workload associated with the thread group is executing on the coprocessor; or perform a hysteretic adjustment of the second control effort parameter to slow a transition of the coprocessor to a low power state while a workload associated with the thread group is executing on the processor.

8. The asymmetric multiprocessor system of claim 7 wherein the hysteretic adjustment of at least one of the first control effort parameter and the second control effort parameter includes delaying a time between the workload being submitted to the coprocessor and decreasing the first control effort parameter.

9. The asymmetric multiprocessor system of claim 7 wherein the hysteretic adjustment includes decreasing a rate at which the first control effort parameter decreases.

10. The asymmetric multiprocessor system of claim 7 wherein the processor is selected from the group consisting of a central processing unit, a graphics processing unit, a general purpose graphics processing unit, a neural engine, an image signal processor, and a scaling and rotating engine.

11. The asymmetric multiprocessor system of claim 7 wherein the coprocessor is selected from the group consisting of a central processing unit, a graphics processing unit, a general purpose graphics processing unit, a neural engine, an image signal processor, and a scaling and rotating engine.

12. The asymmetric multiprocessor system of claim 7 wherein the first and second control effort parameters respectively affect at least one of an allocated subset of cores or execution units and a dynamic voltage and frequency state of the processor or the coprocessor.