Legal claims defining the scope of protection, as filed with the USPTO.
1. A method, comprising: sending, from a processor to a system memory controller, a memory access request comprising a set of parameters including a first parameter indicating a quantity of bits associated with a variable memory page size of a memory array, wherein the system memory controller is coupled to the processor and a local memory controller associated with the memory array, the local memory controller configured to determine the variable memory page size for the memory array based at least in part on the set of parameters; and performing one or more operations according to the memory access request indicating the variable memory page size.
2. The method of claim 1 , wherein: the memory access request comprises one or more read instructions, and the one or more operations comprise receiving data from the local memory controller.
3. The method of claim 1 , wherein: the memory access request comprises one or more write instructions, and the one or more operations comprise sending data to the local memory controller.
4. The method of claim 1 , wherein: the set of parameters includes a second parameter indicating an address associated with a location of data to access.
5. The method of claim 1 , wherein: the system memory controller is configured to send a second set of parameters to the local memory controller based at least in part on the set of parameters, and the second set of parameters comprises an identification of the memory array, an address associated with the memory array, and the variable memory page size.
6. A system, comprising: a system memory controller; a local memory controller in electronic communication with the system memory controller, the local memory controller coupled with a memory array and operable to determine a variable memory page size for the memory array; a processor in electronic communication with the system memory controller and the local memory controller, the processor operable to send a set of parameters including a first parameter indicating a quantity of bits associated with the variable memory page size for the memory array to the system memory controller, wherein the local memory controller is operable to determine the variable memory page size for the memory array based at least in part on the set of parameters; and one or more components in electronic communication with the processor, wherein the processor is operable to access the memory array via the system memory controller and the local memory controller according to the variable memory page size to operate the one or more components, wherein the one or more components comprise at least one of: an input and output (I/O) controller; a peripheral component; or a basic input/output system (BIOS) component.
7. The system of claim 6 , wherein: the processor is operable to send a memory access request that comprises the set of parameters indicative of the variable memory page size to the system memory controller.
8. The system of claim 6 , wherein: the processor is operable to receive data from the local memory controller.
9. The system of claim 6 , wherein: the processor is operable to send data to the local memory controller.
10. The system of claim 6 , wherein: the system memory controller is operable to receive, from the processor, a memory access request that comprises the set of parameters indicative of the variable memory page size.
11. The system of claim 10 , wherein: the system memory controller is operable to configure a memory access command based at least in part on receiving the memory access request, the memory access command comprises a second set of parameters indicative of the variable memory page size and an identification of the memory array, and the second set of parameters is based at least in part on the set of parameters.
12. The system of claim 11 , wherein: the second set of parameters comprises at least one of the identification of the memory array, an address associated with the memory array, or the variable memory page size.
13. The system of claim 11 , wherein: the system memory controller is further operable to send, to the local memory controller, the memory access command with the second set of parameters.
14. The system of claim 11 , wherein: the processor is operable to perform one or more operations according to the memory access request indicating the variable memory page size.
15. The system of claim 6 , wherein: the set of parameters includes a second parameter indicating an address associated with a location of data to access.
16. A system, comprising: a local memory controller associated with a memory array and configured to determine a variable memory page size for the memory array; a system memory controller coupled with the local memory controller; and a processor in electronic communication with the system memory controller and the local memory controller, wherein the processor is configured to: send, to the system memory controller, a memory access request comprising a set of parameters including a first parameter indicating a quantity of bits associated with the variable memory page size for the memory array, wherein the local memory controller is configured to determine the variable memory page size for the memory array based at least in part on the set of parameters; and perform one or more operations according to the memory access request indicating the variable memory page size.
17. The system of claim 16 , wherein: the memory access request comprises one or more read instructions, and the one or more operations comprise receiving data from the local memory controller.
18. The system of claim 16 , wherein: the memory access request comprises one or more write instructions, and the one or more operations comprise sending data to the local memory controller.
19. The system of claim 16 , wherein: the set of parameters includes a second parameter indicating an address associated with a location of data to access.
20. The system of claim 16 , wherein: the system memory controller is configured to send a second set of parameters to the local memory controller based at least in part on the set of parameters, and the second set of parameters comprises an identification of the memory array, an address associated with the memory array, and the variable memory page size.
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October 26, 2021
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