Selectively Supporting Static Branch Prediction Settings Only in Association with Processor-Designated Types of Instructions

1. A processor comprising: a branch prediction mechanism of the processor reading at least one instruction from a memory subsystem, the at least one instruction comprising one of a branch instruction and a non-branch instruction, the at least one instruction initially received by an instruction fetch unit of the processor with static branch prediction setting bits with a primary bit indicating whether a branch should be statically predicted and a secondary bit indicating whether to predict the branch as taking a branch path from among two paths of the branch, wherein a pre-decode unit of the instruction fetch unit recodes the branch instruction with branch direction control bits, wherein the pre-decode unit recodes the branch direction control bits based on the static branch prediction setting bits only in response to an instruction fetch unit of the processor set to operate in a static mode; the branch prediction mechanism, in response to the instruction fetch unit set to operate in a dynamic mode and the branch instruction comprising a conditional branch instruction, dynamically predicting the branch path as taken or not taken from among two paths of the conditional branch instruction based on the branch direction control bits set for the dynamic mode; the branch prediction mechanism, in response to the instruction fetch unit set to operate in the static mode, the branch instruction comprising the conditional branch instruction, and a second bit of the branch direction control bits set to specify static prediction based on the primary bit, statically setting the branch path as taken or not taken according to a first bit of the branch direction control bits set based on the primary bit and the secondary bit of the static branch prediction setting bits; and the branch prediction mechanism selectively setting an operation of the processor temporarily from the dynamic mode to the static mode only in response to detecting a type of the at least one instruction matches a type of instruction qualifying to trigger static branch prediction.

2. The processor according to claim 1 , further comprising: the branch prediction mechanism, in response to detecting a type of a recoded instruction matches the type of instruction qualifying to trigger static branch prediction and detecting the processor is set to operate in a mode for dynamically honoring the static branch prediction setting bits bit settings, determining whether a state bit is set to the static mode; the branch prediction mechanism, in response to determining the state bit is set to the static mode, resetting a counter to a threshold number; the branch prediction mechanism, in response to determining the state bit is not already set to the static mode, setting the state bit to set the operation of the processor to the static mode and setting the counter to the threshold number; the branch prediction mechanism decrementing the counter from the threshold number for each selected branch action detected comprising at least one of a cache line crossed or a taken branch encountered by a branch prediction unit; and the branch prediction mechanism, in response to the counter reaching zero, automatically returning the operation of the instruction fetch unit from the static mode to the dynamic mode.

3. The processor according to claim 1 , further comprising: the branch prediction mechanism detecting a branch prediction unit fetch and the branch instruction matching the type of instruction qualifying to trigger static branch prediction, wherein a recoded instruction comprises a no operation branch instruction.

4. The processor according to claim 1 , further comprising: the branch prediction mechanism detecting, in a decode unit of the instruction fetch unit, fetch of a recoded instruction matching the type of instruction qualifying to trigger static branch prediction, wherein the recoded instruction comprises a load word and reserved index instruction.

5. The processor of claim 1 , further comprising: the pre-decode unit selectively recoding the branch direction control bits for the conditional branch instruction according to the static branch prediction setting bits received with the branch instruction by performing a logical AND operation on the primary bit and the secondary bit, setting the first bit of the branch direction control bits to a first result of the logical AND operation, performing a logical NOT operation on the primary bit, and setting the second bit of the branch direction control bits to a second result of the logical NOT operation.

6. A processor, comprising: an instruction fetch unit of a plurality of functional units of the processor; a pre-decode unit of the instruction fetch unit reading at least one instruction from a memory subsystem, the at least one instruction comprising static branch prediction setting bits comprising a primary bit indicating whether a branch should be statically predicted and a secondary bit indicating whether to predict the branch as taking a branch path from among two paths of the branch; the pre-decode unit selectively recoding each at least one instruction, wherein selectively recoding each at least one instruction comprising a branch instruction comprises adding branch direction control bits specifying handling of the branch instruction by a branch prediction unit of the instruction fetch unit; in response to the pre-decode unit operating in a dynamic mode from among a static mode and a dynamic mode and the branch instruction comprising a conditional branch instruction, the pre-decode unit selectively recoding the branch direction control bits for the conditional branch instruction by setting a first bit of the branch direction control bits to indicate to not predict the conditional branch instruction as always taken from among two paths of the conditional branch instruction and setting a second bit of the branch direction control bits to indicate the conditional branch instruction is designated for dynamic prediction; in response to the pre-decode unit operating in the static mode and the branch instruction comprising the conditional branch instruction, the pre-decode unit selectively recoding the branch direction control bits for the conditional branch instruction according to the static branch prediction setting bits received with the branch instruction by performing a logical AND operation on the primary bit and the secondary bit, setting the first bit of the branch direction control bits to a first result of the logical AND operation, performing a logical NOT operation on the primary bit, and setting the second bit of the branch direction control bits to a second result of the logical NOT operation; and selective branch prediction logic of the instruction fetch unit selectively setting an operation of the processor temporarily from the dynamic mode to the static mode, only in response to fetching the at least one instruction and detecting a type of the recoded instruction matches a type of instruction qualifying to trigger static branch prediction.

7. The processor according to claim 6 , wherein the pre-decode unit selectively recodes the branch direction control bits for the conditional branch instruction according to the static branch prediction setting bits received with the conditional branch instruction only in response to the pre-decode unit operating in the static mode.

8. The processor according to claim 6 , further comprising: the selective branch prediction logic, in response to fetching the at least one instruction, detecting the type of the recoded instruction matches the type of instruction qualifying to trigger static branch prediction, and detecting the processor is set to operate in a mode for dynamically honoring the static branch prediction setting bits, determining whether a state bit is set to the static mode; the selective branch prediction logic, in response to determining the state bit is set to the static mode, resetting a counter to a threshold number, wherein the counter decrements for each selected branch action detected; and the selective branch prediction logic, in response to determining the state bit is not already set to the static mode, setting the state bit to set the operation of the processor to the static mode and setting the counter to the threshold number.

9. The processor according to claim 8 , further comprising: the selective branch prediction logic decrementing the counter from the threshold number for each selected branch action detected comprising at least one of a cache line crossed or a taken branch encountered by the branch prediction unit; and the selective branch prediction logic, in response to the counter decrementing to zero, automatically returning the operation of the processor from the static mode to the dynamic mode.

10. The processor according to claim 8 , further comprising: the selective branch prediction logic detecting a branch prediction unit fetch, from an instruction cache, and the recoded instruction matching the type of instruction qualifying to trigger static branch prediction, wherein the recoded instruction comprises a no operation branch instruction.

11. The processor according to claim 8 , further comprising: the selective branch prediction logic detecting, in a decode unit of the instruction fetch unit, a fetch, from an instruction cache, of the recoded instruction matching the type of instruction qualifying to trigger static branch prediction, wherein the recoded instruction comprises a load word and reserved index instruction.

12. A method, comprising: reading, by a pre-decode unit of an instruction fetch unit of a plurality of functional units of a processor, at least one instruction from a memory subsystem, the at least one instruction comprising static branch prediction setting bits comprising a primary bit indicating whether a branch should be statically predicted and a secondary bit indicating whether to predict the branch as taking a branch path from among two paths of the branch; selectively recoding, by the pre-decode unit, each at least one instruction, wherein selectively recoding each at least one instruction comprising a branch instruction comprises adding branch direction control bits specifying handling of the branch instruction by a branch prediction unit of the instruction fetch unit; in response to the pre-decode unit operating in a dynamic mode from among a static mode and the dynamic mode and the branch instruction comprising a conditional branch instruction, selectively recoding, by the pre-decode unit, the branch direction control bits for the conditional branch instruction by setting a first bit of the branch direction control bits to indicate to not predict the conditional branch instruction as always taken from among two paths of the conditional branch instruction and setting a second bit of the branch direction control bits to indicate the conditional branch instruction is designated for dynamic prediction; in response to the pre-decode unit operating in the static mode and the branch instruction comprising the conditional branch instruction, selectively recoding, by the pre-decode unit, the branch direction control bits for the conditional branch instruction according to the static branch prediction setting bits received with the branch instruction by performing a logical AND operation on the primary bit and the secondary bit, setting the first bit of the branch direction control bits to a first result of the logical AND operation, performing a logical NOT operation on the primary bit, and setting the second bit of the branch direction control bits to a second result of the logical NOT operation; and selectively setting, by selective branch prediction logic of the instruction fetch unit, an operation of the processor temporarily from the dynamic mode to the static mode, only in response to fetching the at least one instruction and detecting a type of the recoded instruction matches a type of instruction qualifying to trigger static branch prediction.

13. The method according to claim 12 , further comprising: selectively recoding, by the pre-decode unit, the branch direction control bits for the conditional branch instruction according to the static branch prediction setting bits received with the conditional branch instruction only in response to the pre-decode unit operating in the static mode.

14. The method according to claim 12 , further comprising: in response to fetching the at least one instruction, detecting, by the selective branch prediction logic, the type of the recoded instruction matches the type of instruction qualifying to trigger static branch prediction, and detecting the processor is set to operate in a mode for dynamically honoring the static branch prediction setting bits, determining whether a state bit is set to the static mode; in response to determining the state bit is set to the static mode, resetting, by the selective branch prediction logic, a counter to a threshold number, wherein the counter decrements for each selected branch action detected; and in response to determining the state bit is not already set to the static mode, setting, by the selective branch prediction logic, the state bit to set the operation of the processor to the static mode and setting the counter to the threshold number.

15. The method according to claim 14 , further comprising: decrementing, by the selective branch prediction logic, the counter from the threshold number for each selected branch action detected comprising at least one of a cache line crossed or a taken branch encountered by the branch prediction unit; and in response to the counter decrementing to zero, automatically returning, by the selective branch prediction logic, the operation of the processor from the static mode to the dynamic mode.

16. The method according to claim 14 , further comprising: detecting, by the selective branch prediction logic, a branch prediction unit fetch, from an instruction cache, and the recoded instruction matching the type of instruction qualifying to trigger static branch prediction, wherein the recoded instruction comprises a no operation branch instruction.

17. The method according to claim 14 , further comprising: detecting, by the selective branch prediction logic, in a decode unit, of the instruction fetch unit, a fetch, from an instruction cache, of the recoded instruction matching the type of instruction qualifying to trigger static branch prediction, wherein the recoded instruction comprises a load word and reserved index instruction.