Systems, Devices, and Methods for Data Migration

1. A method, comprising: receiving, from a host device via a sideband channel that couples the host device with a controller of a memory system, a first command to transfer a first data set between a first bank of a first memory device of the memory system and a second memory device of the memory system, wherein the sideband channel is different than a command/address bus or data bus that couples the host device with the first memory device of the memory system; transmitting, to the first memory device based at least in part on the first command, a second command to transfer at least a portion of the first data set between the first bank of the first memory device and the second memory device, wherein the second command is to be executed concurrent with an access command to transfer a second data set between the host device and a second bank of the first memory device different than the first bank; receiving, from the first memory device, an indication of an execution of the access command and an execution of the second command concurrent with the execution of the access command; and transmitting, via the sideband channel to the host device, a second indication of an execution of the first command.

2. The method of claim 1 , wherein receiving the first command comprises: receiving the first command from the first memory device via an interface for communicating with the first memory device.

3. The method of claim 1 , further comprising: determining that the first command corresponds to a transfer of more than one data set, wherein a single transfer of one data set corresponds to a data transfer between a single bank of the first memory device and the second memory device.

4. The method of claim 3 , further comprising: mapping an address associated with the first command to the first bank of the first memory device, wherein the determining that the first command corresponds to more than one transfer of data is based at least in part on mapping the address to the first bank.

5. The method of claim 1 , wherein the first command corresponds to a commit command that indicates that at least the portion of the first data set is to be transferred from the second memory device to the first bank of the first memory device.

6. The method of claim 1 , wherein the first command corresponds to an evict command that indicates that at least the portion of the first data set is to be transferred from the first bank of the first memory device to the second memory device.

7. The method of claim 1 , wherein the first data set corresponds to a portion of a page of data.

8. A method, comprising: receiving a first command to transfer a first data set between a first bank of a first memory device of a memory system and a second memory device of the memory system, wherein the first command corresponds to a commit command that indicates that at least a portion of the first data set is to be transferred from the second memory device to the first bank of the first memory device; transmitting the commit command to the second memory device via an interface for communicating with the second memory device; receiving the first data set from the second memory device; dividing the first data set into portions of data based at least in part on a determination that an access command to transfer a second data set between a host device and a second bank of the first memory device different than the first bank corresponds to more than one transaction of data; transferring each of the portions of data from a controller to a buffer associated with the first memory device; transmitting, to the first memory device based at least in part on the first command, a second command to be executed concurrent with the access command, wherein transmitting the second command comprises transferring at least one of the portions of data; and receiving, from the first memory device, an indication of an execution of the access command and an execution of the second command concurrent with the execution of the access command.

9. The method of claim 8 , wherein transferring each of the portions of data from the controller to the buffer further comprises: transferring a first portion of data to the buffer; and transferring a second portion of data to the buffer based at least in part on receiving the indication of the execution of the access command, wherein the indication indicates that the buffer is available.

10. A method, comprising: receiving a first command to transfer a first data set between a first bank of a first memory device of a memory system and a second memory device of the memory system, wherein the first command corresponds to an evict command that indicates that at least a portion of the first data set is to be transferred from the first bank of the first memory device to the second memory device; transmitting, to the first memory device based at least in part on the first command, a second command to be executed concurrent with an access command to transfer a second data set between a host device and a second bank of the first memory device different than the first bank; receiving the first data set from the first memory device based at least in part on transmitting the second command; receiving, from the first memory device, an indication of an execution of the access command and an execution of the second command concurrent with the execution of the access command, wherein the indication indicates that at least the portion of the first data set has been transferred from the first memory device to a buffer associated with a controller; and transferring the first data set from the controller to the second memory device based at least in part on receiving the indication of the execution of the access command.

11. The method of claim 10 wherein receiving the first data set from the first memory device further comprises: dividing the first command into sub-commands corresponding to portions of the first data set associated with a single bank, wherein the second command comprises a sub-command for evicting a portion of data from the single bank; receiving, from the first memory device, a first portion of the first data set; and transmitting, to the first memory device, a third command including a second sub-command, wherein transmitting the third command is based at least in part on receiving the indication of the execution of the access command.

12. A controller, comprising: a first interface configured to communicate with a first memory device of a memory system, the first memory device comprising memory cells of a first type; a second interface configured to communicate with a second memory device of the memory system, the second memory device comprising memory cells of a second type different than the first type; a queue coupled with the first interface and configured to receive a command for transferring data between the first memory device and the second memory device via a sideband channel; a third interface configured to communicate with a host device via the sideband channel that couples the host device with the controller, wherein the sideband channel is different than a command/address bus or data bus that couples the host device with the first memory device of the memory system, and wherein the controller is configured to transfer an update command status indicating an execution of the command, via the sideband channel, to the host device; a first buffer coupled with the first interface and the second interface and configured to store data to be transferred from the second memory device to a first bank of the first memory device as part of a data migration operation that is executed concurrent with the host device accessing a second bank of the first memory device different than the first bank of the first memory device; and a second buffer coupled with the first interface and the second interface and configured to store data to be transferred from the first bank of the first memory device to the second memory device as part of the data migration operation.

13. The controller of claim 12 , wherein the queue is configured to receive the command via the first interface.

14. The controller of claim 13 , wherein the controller is configured to receive, from the first memory device via the first interface, an indication of an execution of an access command for transferring data between the first memory device and the host device.

15. The controller of claim 12 , wherein the controller is configured to map an address indicated by the command to one or more banks within the first memory device.

16. An apparatus, comprising: a first interface to communicate with a first memory device of a memory system, the first memory device comprising memory cells of a first type; a second interface to communicate with a second memory device of the memory system, the second memory device comprising memory cells of a second type different than the first type; a controller operable to; receive, from a host device via a sideband channel that couples the host device with the controller of the memory system, a first command to transfer a first data set between a first bank of the first memory device and the second memory device, wherein the sideband channel is different than a command/address bus or data bus that couples the host device with the first memory device; transmit, to the first memory device based at least in part on receiving the first command, a second command to transfer at least a portion of the first data set between the first bank of the first memory device and the second memory device, wherein the second command is be executed concurrently with an access command to transfer a second data set between the host device and a second bank different than the first bank; and receive, from the first memory device, an indication of an execution of the access command and an execution of the second command concurrent with the execution of the access command; and transmit, via the sideband channel to the host device, a second indication of an execution of the first command.

17. The apparatus of claim 16 , wherein the controller is further operable to: receive the first command from the first memory device via the first interface.

18. The apparatus of claim 16 , wherein the controller is further operable to: determine that the first command corresponds to a transfer of more than one data set, wherein a transfer of one data set corresponds to a data transfer between a single bank of the first memory device and the second memory device.