Techniques For Link Partner Error Reporting

1. Hardware integrated circuitry for use in a network switch for being coupled to at least one Ethernet protocol network link partner via at least one Ethernet protocol link, the hardware integrated circuitry comprising: at least one machine-readable memory; hardware transceiver circuitry to be coupled via the at least one Ethernet protocol link to the at least one Ethernet protocol link partner, the hardware transceiver circuitry to be used in Ethernet protocol frame communication to be carried out between the network switch and the at least one network link partner via the at least one Ethernet protocol link; wherein, when the network switch is in operation, the hardware integrated circuitry is to perform operations comprising: determining error information associated with received Ethernet protocol frame data, the error information comprising respective counts of codewords of the received Ethernet protocol frame data that include respective numbers of symbol errors, the respective counts of codewords comprising: a first count of codewords of the received Ethernet protocol frame data that include a first number of symbol errors; and a second count of codewords of the received Ethernet protocol frame data that include a second number of symbol errors, the second number of symbol errors being greater than the first number of symbol errors; and storing the error information in the at least one machine-readable memory.

2. The hardware integrated circuitry of claim 1 , wherein: the respective counts of codewords comprise fifteen respective counts of codewords; the respective numbers of symbol errors comprise fifteen respective numbers of symbol errors; and the respective numbers of symbol errors are mutually different from each other.

3. The hardware integrated circuitry of claim 2 , wherein: the codewords of the received Ethernet protocol frame data comprise forward error correction (FEC) codewords; and the hardware integrated circuitry comprises Reed-Solomon decoder circuitry for use in association with the error information.

4. The hardware integrated circuitry of claim 3 , wherein: when the network switch is in the operation, the network switch is to provide the error information to a network node for use in association with network management.

5. The hardware integrated circuitry of claim 3 , wherein: when the network switch is in the operation, the network switch is to provide the error information to the at least one Ethernet protocol link partner via the at least one Ethernet protocol link.

6. The hardware integrated circuitry of claim 3 , wherein when the network switch is in the operation: parameters associated with the respective numbers of symbol errors are configurable; and following reading of the respective counts of codewords, the respective counts of codewords are to be cleared.

7. The hardware integrated circuitry of claim 3 , wherein: another network switch comprises the at least one Ethernet protocol link partner.

8. The hardware integrated circuitry of claim 3 , wherein: the network switch is for use in router applications.

9. Non-transitory computer-readable storage medium storing instructions for being executed by hardware integrated circuitry, the hardware integrated circuitry being for use in a network switch, the network switch for being coupled to at least one Ethernet protocol network link partner via at least one Ethernet protocol link, the hardware integrated circuitry comprising at least one machine-readable memory and hardware transceiver circuitry, the hardware transceiver circuitry to be coupled via the least one Ethernet protocol link to the at least one Ethernet protocol network link partner, the instructions, when executed by the hardware integrated circuitry, resulting in the hardware integrated circuitry being configured to perform operations comprising: carrying out, using the hardware transceiver circuitry, Ethernet protocol frame communication between the network switch and the at least one network link partner via the at least one Ethernet protocol link; determining error information associated with received Ethernet protocol frame data, the error information comprising respective counts of codewords of the received Ethernet protocol frame data that include respective numbers of symbol errors, the respective counts of codewords comprising: a first count of codewords of the received Ethernet protocol frame data that include a first number of symbol errors; and a second count of codewords of the received Ethernet protocol frame data that include a second number of symbol errors, the second number of symbol errors being greater than the first number of symbol errors; and storing the error information in the at least one machine-readable memory.

10. The non-transitory computer-readable storage medium of claim 9 , wherein: the respective counts of codewords comprise fifteen respective counts of codewords; the respective numbers of symbol errors comprise fifteen respective numbers of symbol errors; and the respective numbers of symbol errors are mutually different from each other.

11. The non-transitory computer-readable storage medium of claim 10 , wherein: the codewords of the received Ethernet protocol frame data comprise forward error correction (FEC) codewords; and the hardware integrated circuitry comprises Reed-Solomon decoder circuitry for use in association with the error information.

12. The non-transitory computer-readable storage medium of claim 10 , wherein: when the network switch is in the operation, the network switch is to provide the error information to a network node for use in association with network management.

13. The non-transitory computer-readable storage medium of claim 10 , wherein: when the network switch is in the operation, the network switch is to provide the error information to the at least one Ethernet protocol link partner via the at least one Ethernet protocol link.

14. The non-transitory computer-readable storage medium of claim 10 , wherein when the network switch is in the operation: parameters associated with the respective numbers of symbol errors are configurable; and following reading of the respective counts of codewords, the respective counts of codewords are to be cleared.

15. The non-transitory computer-readable storage medium of claim 10 , wherein: another network switch comprises the at least one Ethernet protocol link partner.

16. The non-transitory computer-readable storage medium of claim 10 , wherein: the network switch is for use in router applications.

17. A method implemented by hardware integrated circuitry, the hardware integrated circuitry being for use in a network switch, the network switch for being coupled to at least one Ethernet protocol network link partner via at least one Ethernet protocol link, the hardware integrated circuitry comprising at least one machine-readable memory and hardware transceiver circuitry, the hardware transceiver circuitry to be coupled via the least one Ethernet protocol link to the at least one Ethernet protocol network link partner, the method comprising: carrying out, using the hardware transceiver circuitry, Ethernet protocol frame communication between the network switch and the at least one network link partner via the at least one Ethernet protocol link; determining error information associated with received Ethernet protocol frame data, the error information comprising respective counts of codewords of the received Ethernet protocol frame data that include respective numbers of symbol errors, the respective counts of codewords comprising: a first count of codewords of the received Ethernet protocol frame data that include a first number of symbol errors; and a second count of codewords of the received Ethernet protocol frame data that include a second number of symbol errors, the second number of symbol errors being greater than the first number of symbol errors; and storing the error information in the at least one machine-readable memory.

18. The method of claim 17 , wherein: the respective counts of codewords comprise fifteen respective counts of codewords; the respective numbers of symbol errors comprise fifteen respective numbers of symbol errors; and the respective numbers of symbol errors are mutually different from each other.

19. The method of claim 18 , wherein: the codewords of the received Ethernet protocol frame data comprise forward error correction (FEC) codewords; and the hardware integrated circuitry comprises Reed-Solomon decoder circuitry for use in association with the error information.

20. The method of claim 18 , wherein: when the network switch is in the operation, the network switch is to provide the error information to a network node for use in association with network management.

21. The method of claim 18 , wherein: when the network switch is in the operation, the network switch is to provide the error information to the at least one Ethernet protocol link partner via the at least one Ethernet protocol link.

22. The method of claim 18 , wherein when the network switch is in the operation: parameters associated with the respective numbers of symbol errors are configurable; and following reading of the respective counts of codewords, the respective counts of codewords are to be cleared.

23. The method of claim 18 , wherein: another network switch comprises the at least one Ethernet protocol link partner.

24. The method of claim 18 , wherein: the network switch is for use in router applications.

25. Hardware integrated circuitry for use in association with at least one Ethernet protocol network link partner coupled to at least one Ethernet protocol link, the hardware integrated circuitry comprising: at least one machine-readable memory; hardware transceiver circuitry to be coupled via the at least one Ethernet protocol link to the at least one Ethernet protocol link partner, the hardware transceiver circuitry to be used in Ethernet protocol frame communication to be carried out with the at least one network link partner via the at least one Ethernet protocol link; wherein, when the hardware integrated circuitry is in operation, the hardware integrated circuitry is to perform operations comprising: determining error information associated with received Ethernet protocol frame data, the error information comprising respective counts of codewords of the received Ethernet protocol frame data that include respective numbers of symbol errors, the respective counts of codewords comprising: a first count of codewords of the received Ethernet protocol frame data that include a first number of symbol errors; and a second count of codewords of the received Ethernet protocol frame data that include a second number of symbol errors, the second number of symbol errors being greater than the first number of symbol errors; and storing the error information in the at least one machine-readable memory.

26. The hardware integrated circuitry of claim 25 , wherein: the respective counts of codewords comprise fifteen respective counts of codewords; the respective numbers of symbol errors comprise fifteen respective numbers of symbol errors; and the respective numbers of symbol errors are mutually different from each other.

27. The hardware integrated circuitry of claim 26 , wherein: the codewords of the received Ethernet protocol frame data comprise forward error correction (FEC) codewords; and the hardware integrated circuitry comprises Reed-Solomon decoder circuitry for use in association with the error information.

28. Non-transitory computer-readable storage medium storing instructions for being executed by hardware integrated circuitry, the hardware integrated circuitry being for use in association with at least one Ethernet protocol network link partner coupled to at least one Ethernet protocol link, the hardware integrated circuitry comprising at least one machine-readable memory and hardware transceiver circuitry, the hardware transceiver to be coupled via the at least one Ethernet protocol link to the at least one Ethernet protocol link partner, the instructions, when executed by the hardware integrated circuitry, resulting in the hardware integrated circuitry being configured to perform operations comprising: carrying out, using the hardware transceiver circuitry, Ethernet protocol frame communication with the at least one network link partner via the at least one Ethernet protocol link; determining error information associated with received Ethernet protocol frame data, the error information comprising respective counts of codewords of the received Ethernet protocol frame data that include respective numbers of symbol errors, the respective counts of codewords comprising: a first count of codewords of the received Ethernet protocol frame data that include a first number of symbol errors; and a second count of codewords of the received Ethernet protocol frame data that include a second number of symbol errors, the second number of symbol errors being greater than the first number of symbol errors; and storing the error information in the at least one machine-readable memory.

29. The non-transitory computer-readable memory of claim 28 , wherein: the respective counts of codewords comprise fifteen respective counts of codewords; the respective numbers of symbol errors comprise fifteen respective numbers of symbol errors; and the respective numbers of symbol errors are mutually different from each other.

30. The non-transitory computer-readable memory of claim 29 , wherein: the codewords of the received Ethernet protocol frame data comprise forward error correction (FEC) codewords; and the hardware integrated circuitry comprises Reed-Solomon decoder circuitry for use in association with the error information.

31. A method implemented by hardware integrated circuitry, the hardware integrated circuitry being for use in association with at least one Ethernet protocol network link partner coupled to at least one Ethernet protocol link, the hardware integrated circuitry comprising at least one machine-readable memory and hardware transceiver circuitry, the hardware transceiver to be coupled via the at least one Ethernet protocol link to the at least one Ethernet protocol link partner, the method comprising: carrying out, using the hardware transceiver circuitry, Ethernet protocol frame communication with the at least one network link partner via the at least one Ethernet protocol link; determining error information associated with received Ethernet protocol frame data, the error information comprising respective counts of codewords of the received Ethernet protocol frame data that include respective numbers of symbol errors, the respective counts of codewords comprising: a first count of codewords of the received Ethernet protocol frame data that include a first number of symbol errors; and a second count of codewords of the received Ethernet protocol frame data that include a second number of symbol errors, the second number of symbol errors being greater than the first number of symbol errors; and storing the error information in the at least one machine-readable memory.

32. The method of claim 31 , wherein: the respective counts of codewords comprise fifteen respective counts of codewords; the respective numbers of symbol errors comprise fifteen respective numbers of symbol errors; and the respective numbers of symbol errors are mutually different from each other.

33. The method of claim 32 , wherein: the codewords of the received Ethernet protocol frame data comprise forward error correction (FEC) codewords; and the hardware integrated circuitry comprises Reed-Solomon decoder circuitry for use in association with the error information.