System-In-Package Network Processors

1. An integrated circuit device comprising: a base die that comprises memory; and a programmable fabric die coupled to the base die via a high-speed interface, wherein the programmable fabric die and the base die are vertically aligned so the base die is vertically below at least a portion of a surface area of the programmable fabric die with a sector of the programmable fabric die being vertically aligned with a corresponding sector-aligned memory of the memory of the base die that is allocated to the sector, the programmable fabric die comprising a first configuration loaded into the programmable fabric of the programmable fabric die to implement a network function block in the programmable fabric die that performs a network processing function, wherein the network processing function employs a data structure for performance of the network processing function or a data packet to be processed by the network processing function, or both, and wherein the base die stores the data structure, the data packet, or both, and wherein the programmable fabric die is configured to perform operations using data in the memory.

2. The integrated circuit device of claim 1 , wherein the high-speed interface comprises a high density interconnect, a 3D interconnect, or a microbump interconnect.

3. The integrated circuit device of claim 1 , wherein the programmable fabric die comprises a plurality of sectors and the base die comprises sector-aligned memory circuitries, and wherein the network function block is disposed in one sector of the plurality of sectors or in a subplurality of the plurality of sectors.

4. The integrated circuit device of claim 3 , wherein the network function block is disposed in a first sector and the data structure or data packet is disposed in a first sector-aligned memory circuitry associated with the first sector.

5. The integrated circuit device of claim 3 , wherein the network function block is disposed in a first sector, the data structure is disposed in a second sector-aligned memory, and the network function block accesses the data structure using a network-on-chip (NOC) of the base die.

6. The integrated circuit device of claim 1 , wherein the memory of the base die comprises configuration data used to load in a second configuration to implement a second network function block in the programmable fabric, and wherein the programmable fabric die is configurable to perform partial reconfiguration by programming a portion of the programmable fabric with the configuration data for the second network function block.

7. The integrated circuit device of claim 6 , wherein programming the portion of the programmable fabric die comprises replacing the network function block with the second network function block.

8. The integrated circuit device of claim 1 , wherein the network function block comprises a quality of service (QoS) functionality, a packet filtering functionality, a packet routing, an encryption functionality, a decryption functionality, an error checking functionality, a direct memory access management functionality, or a look-up table functionality, or a combination thereof.

9. A system comprising: a memory; and a network processor comprising: a base die that comprises on-package memory comprising a plurality of regions; and a processor die having a plurality of programmable sectors, wherein the processor die and the base die are vertically aligned so the base die is vertically below at least a portion of a surface area of the processor die with the plurality of regions vertically aligned to corresponding sectors of the plurality of programmable sectors, and the network processor is operable to execute processes using data from the base die, wherein the network processor is configured to: implement a first network function configured to exchange data with the on-package memory in the base die using a high-speed interface between the processor die and the base die when a first configuration is loaded into the network processor; and utilize buffer manager circuitry configured to exchange data with the memory.

10. The system of claim 9 , wherein the processor die comprises an application-specific integrated circuit (ASIC), programmable fabric, a field programmable gate array (FPGA), or a general-purpose processor, or any combination thereof.

11. The system of claim 9 , wherein the first network function is configured to process header data, and wherein the buffer manager circuitry processes payload data and stores a link data structure that associates a header of the header data with a payload of the payload data.

12. The system of claim 9 , wherein the buffer manager circuitry exchanges payloads with the memory or references to payloads with the memory.

13. The system of claim 9 , wherein the processor die comprises programmable fabric, the on-package memory comprises configuration data specifying a second configuration that is loadable into the network processor to implement a second network function, and the network processor is configurable to swap the first network function for the second network function in the programmable fabric by configuring programmable fabric with the second network function using partial reconfiguration of the programmable fabric.

14. The system of claim 9 , wherein the network processor comprises Ethernet circuitry, peripheral component interconnect express (PCIe) circuitry, Fibre Channel network circuitry, Infiniband circuitry, remote direct memory access (RDMA) circuitry, converged ethernet circuitry, or synchronous optical network (SONET) circuitry, or any combination thereof.

15. The system of claim 9 , wherein the network processor comprises a data bridge that receives data in a first protocol and transmits data in a second protocol different from the first protocol.

16. The system of claim 9 , wherein the network processor comprises a network interface card (NIC), a host bus adapter (HBA), a converged network adapter (CNA).

17. The system of claim 9 , wherein the system comprises a data center, or a storage center, or both.

18. A method for virtualization of a network device that comprises a programmable fabric device, the method comprising: receiving, in the programmable fabric device, a request to replace a first network processing function implemented using a first configuration loaded into a programmable fabric of the programmable fabric device by loading a second configuration corresponding to a second network processing function into the programmable fabric, wherein a programmable fabric die of the programmable fabric device comprises the first network processing function and a base die of the programmable fabric device contains on-package memory that comprises configuration data specifying a second configuration used to implement the second network processing function; retrieving, by the programmable fabric die, the configuration data for the second network processing function from the on-package memory over a high-speed interface that connects the base die and the programmable fabric die, wherein the programmable fabric die and the base die are vertically aligned so the base die is vertically below at least a portion of a surface area of the programmable fabric die with a sector of the programmable fabric die implementing the second configuration being vertically aligned with a corresponding sector-aligned memory of the base die storing the second configuration; and programming, by the programmable fabric die, a portion of the programmable fabric die with the configuration data for the second network processing function during operation of the programmable fabric device.

19. The method of claim 18 , wherein the programmable fabric device comprises a first virtual network function (VNF) profile that comprises the first network processing function and a second VNF profile that comprises the second network processing function, and wherein the request comprises a swap of the first VNF profile by the second VNF profile.

20. The method of claim 18 , wherein the high-speed interface comprises a microbump interface.

21. The method of claim 18 , wherein retrieving the configuration data comprises accessing the configuration data using a network-on-chip (NOC) of the base die.

22. The method of claim 18 , comprising loading a data structure associated with the second network processing function into a sector-aligned memory of the base die.

23. The method of claim 18 , wherein the programmable fabric die comprises a sector manager configured to receive the request.