Resource Allocation for Reconfigurable Processors

1. A data processing system, comprising: a pool of reconfigurable dataflow resources, reconfigurable dataflow resources in the pool of reconfigurable dataflow resources including a plurality of reconfigurable processors operatively coupled by links, and the links having rated link bandwidths and rated link latencies; and runtime logic operatively coupled to the pool of reconfigurable dataflow resources, and configured to: receive, for a first application, a first plurality of configuration files, a first configuration of a first plurality of virtual reconfigurable processors required to execute the first application, and virtual links between virtual reconfigurable processors in the first plurality of virtual reconfigurable processors, wherein the first configuration is encoded in a first virtual routing table that specifies a set of virtual links for each pair of virtual reconfigurable processors in the first plurality of virtual reconfigurable processors, and a first specification of target link bandwidths and target link latencies of the virtual links between the virtual reconfigurable processors in the first plurality of virtual reconfigurable processors; allocate pairs of reconfigurable processors in the plurality of reconfigurable processors to pairs of virtual reconfigurable processors in the first plurality of virtual reconfigurable processors, and links in the set of links to virtual links in the set of virtual links based on: a link bandwidth comparison that compares target link bandwidths of the virtual links in the set of virtual links against rated link bandwidths of the links in the set of links, and a link latency comparison that compares target link latencies of the virtual links in the set of virtual links against rated link latencies of the links in the set of links; and configure the allocated pairs of reconfigurable processors and the allocated links with the configuration data in the first plurality of configuration files, and execute the first application using the configured pairs of reconfigurable processors and the configured links.

2. The data processing system of claim 1 , wherein the first specification is encoded in the first virtual routing table that specifies a target link bandwidth and a target link latency of each virtual link in the set of virtual links.

3. The data processing system of claim 1 , wherein the runtime logic is further configured to receive, for the first application, the routing table that specifies a set of links for each pair of reconfigurable processors in the plurality of reconfigurable processors available to execute the first application.

4. The data processing system of claim 3 , wherein the routing table specifies a rated link bandwidth and a rated link latency of each link in the set of links.

5. The data processing system of claim 3 , wherein the routing table is generated by a resource manager.

6. The data processing system of claim 1 , wherein the runtime logic is further configured to: receive, for a second application, a second plurality of configuration files, a second configuration of a second plurality of virtual reconfigurable processors required to execute the second application, and virtual links between virtual reconfigurable processors in the second plurality of virtual reconfigurable processors, and a second specification of target link bandwidths and target link latencies of the virtual links between the virtual reconfigurable processors in the second plurality of virtual reconfigurable processors.

7. The data processing system of claim 6 , wherein the runtime logic is further configured to: receive, for the second application, revised link bandwidths and revised link latencies of the allocated links, wherein the revised link bandwidths and the revised link latencies result from allocation of parts of the rated link bandwidths and the rated link latencies to the first application; further allocate the allocated reconfigurable processors to the virtual reconfigurable processors in the second plurality of virtual reconfigurable processors, and the allocated links to the virtual links between the virtual reconfigurable processors in the second plurality of virtual reconfigurable processors based on: a link bandwidth comparison that compares the target link bandwidths, specified by the second specification, against the revised link bandwidths, and a link latency comparison that compares the target link latencies, specified by the second specification, against the revised link latencies; and configure the allocated reconfigurable processors and the allocated links with configuration data in the second plurality of configuration files, and execute the second application using the configured reconfigurable processors and the configured links.

8. The data processing system of claim 1 , wherein the first and second pluralities of configuration files, the first and second configurations, and the first and second specifications are generated by a compiler.

9. The data processing system of claim 1 , wherein the rated link latencies are rated based on a number of hops between two reconfigurable processors in the plurality of reconfigurable processors.

10. The data processing system of claim 9 , wherein a hop is an intermediate reconfigurable processor between the two reconfigurable processors.

11. The data processing system of claim 10 , wherein rated link latencies of a set of links between the two reconfigurable processors are normalized scores that are normalized across links in the set of links and thereby sum to a ceiling score.

12. The data processing system of claim 11 , wherein target link latencies of a set of virtual links between two virtual reconfigurable processors are normalized scores that are normalized across virtual links in the set of virtual links and thereby sum to the ceiling score.

13. The data processing system of claim 1 , wherein the rated link bandwidths are rated based on a hardware configuration of the links.

14. The data processing system of claim 13 , wherein the hardware configuration is a data transfer rate of the links.

15. The data processing system of claim 13 , wherein the hardware configuration is a link width of the links.

16. The data processing system of claim 1 , wherein the first and second applications are executed in parallel using the configured reconfigurable processors and the configured links.

17. The data processing system of claim 16 , wherein execution of the first application using the configured reconfigurable processors and the configured links further includes processing and streaming application data for the first application and outputs generated therefor using the configured reconfigurable processors and the configured links.

18. The data processing system of claim 16 , wherein execution of the second application using the configured reconfigurable processors and the configured links further includes processing and streaming application data for the second application and outputs generated therefor using the configured reconfigurable processors and the configured links.

19. The data processing system of claim 1 , wherein the allocated reconfigurable processors are on a same processing node.

20. The data processing system of claim 1 , wherein the allocated reconfigurable processors are on different processing nodes.

21. The data processing system of claim 1 , wherein the link bandwidth comparison precedes the link latency comparison.

22. The data processing system of claim 1 , wherein the link latency comparison precedes the link bandwidth comparison.

23. The data processing system of claim 1 , wherein a unit used to measure and compare the rated link bandwidths and the target link bandwidths is same.

24. The data processing system of claim 1 , wherein a unit used to measure and compare the rated link latencies and the target link latencies is same.

25. A data processing system, comprising: a processor coupled to a memory; a pool of reconfigurable dataflow resources, reconfigurable dataflow resources in the pool of reconfigurable dataflow resources including a plurality of reconfigurable processors operatively coupled by links, and the links having rated link bandwidths and rated link latencies; and runtime logic implemented on the processor and operatively coupled to the pool of reconfigurable dataflow resources, the runtime logic configured to: receive: configuration files for first and second applications, a first virtual routing table that specifies a first plurality of virtual reconfigurable processors required to execute the first application, and target link bandwidths and target link latencies of virtual links between the virtual reconfigurable processors in the first plurality of virtual reconfigurable processors, wherein the first virtual routing table further specifies a set of virtual links for each pair of virtual reconfigurable processors in the first plurality of virtual reconfigurable processors, and a second virtual routing table that specifies a second plurality of virtual reconfigurable processors required to execute the second application, and target link bandwidths and target link latencies of virtual links between the virtual reconfigurable processors in the second plurality of virtual reconfigurable processors, wherein the second virtual routing table further specifies a set of virtual links for each pair of virtual reconfigurable processors in the second plurality of virtual reconfigurable processors; allocate pairs of reconfigurable processors in the plurality of reconfigurable processors to pairs of virtual reconfigurable processors in the first plurality of virtual reconfigurable processors and pairs of reconfigurable processors in the plurality of reconfigurable processors to pairs of virtual reconfigurable processors in the second plurality of virtual reconfigurable processors, and links between reconfigurable processors in the set of reconfigurable processors to the virtual links between the virtual reconfigurable processors in the first plurality of virtual reconfigurable processors and the virtual links between the virtual reconfigurable processors in the second plurality of virtual reconfigurable processors based on: a link bandwidth comparison that compares the rated link bandwidths against the target link bandwidths specified by the first virtual routing table and the target link bandwidths specified by the second virtual routing table, and a link latency comparison that compares the rated link latencies against the target link latencies specified by the first virtual routing table and the target link latencies specified by the second virtual routing table; and configure the allocated pairs of reconfigurable processors and the allocated links with the configuration data in the configuration files, and execute the first and second applications using the configured pairs of reconfigurable processors and the configured links.

26. A data processing system, comprising: a processor coupled to a memory; a pool of reconfigurable dataflow resources, reconfigurable dataflow resources in the pool of reconfigurable dataflow resources including a plurality of reconfigurable processors operatively coupled by links, and the links having rated link bandwidths and rated link latencies; and runtime logic implemented in the processor and operatively coupled to the pool of reconfigurable dataflow resources, the runtime logic configured to: receive, configuration files that define an application, a configuration of a plurality virtual reconfigurable processors and virtual links between the plurality of virtual reconfigurable processors required to execute the application, wherein the configuration is encoded in a virtual routing table that specifies a set of virtual links for each pair of virtual reconfigurable processors in the plurality of virtual reconfigurable processors, and a specification of target link bandwidths and target link latencies of the virtual links; allocate pairs of reconfigurable processors in the plurality of reconfigurable processors to pairs of virtual reconfigurable processors in the plurality of virtual reconfigurable processors, and links in the set of links to virtual links in the set of virtual links based on: a link bandwidth comparison that compares target link bandwidths of the virtual links in the set of virtual links against rated link bandwidths of the links in the set of links, and a link latency comparison that compares target link latencies of the virtual links in the set of virtual links against rated link latencies of the links in the set of links; and configure the allocated pairs of reconfigurable processors and the allocated links with the configuration data in the first plurality of configuration files, and execute the application using the configured pairs of reconfigurable processors and the configured links.